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LH5P832 Datasheet

  • LH5P832

  • CMOS 256K (32K x 8) Pseudo-Static RAM

  • 9頁

  • SHARP

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LH5P832
FEATURES
鈥?/div>
32,768
脳
8 bit organization
鈥?/div>
Access time: 100/120 ns (MAX.)
鈥?/div>
Cycle time: 160/190 ns (MIN.)
鈥?/div>
Power consumption:
Operating: 357.5/303 mW
Standby: 16.5 mW
鈥?/div>
TTL compatible I/O
鈥?/div>
256 refresh cycle/4 ms
鈥?/div>
Auto refresh is executed by internal
counter (controlled by OE/RFSH pin)
鈥?/div>
Self refresh is executed by internal timer
鈥?/div>
Single +5 V power supply
鈥?/div>
Packages:
28-pin, 600-mil DIP
28-pin, 300-mil SK-DIP
28-pin, 450-mil SOP
DESCRIPTION
The LH5P832 is a 256K bit Pseudo-Static RAM or-
ganized as 32,768
脳
8 bits. It is fabricated using sili-
con-gate CMOS process technology.
The LH5P832 uses convenient on-chip refresh cir-
cuitry with a DRAM memory cell for pseudo static
operation. This simplifies external clock inputs, while
providing the same simple, non-multiplexed pinout as
industry standard SRAMs. Moreover, due to the func-
tional similarities between PSRAMs and SRAMs, many
32K
脳
8 SRAM sockets can be filled with the LH5P832
with little or no changes. The advantage is the cost
savings realized with the lower cost PSRAM.
CMOS 256K (32K
脳
8) Pseudo-Static RAM
The LH5P832 PSRAM has the ability to fill the gap
between DRAM and SRAM by offering low cost, low
standby power, and a simple interface.
Three methods of refresh control are provided for
maximum versatility. A 鈥楥E-Only鈥?refresh cycle re-
freshes the addressed row of memory cells transpar-
ently. All 256 rows must be refreshed or accessed every
four milliseconds. 鈥楢uto Refresh鈥?automatically cycles
through a different row on every OE/RFSH clock pulse,
accomplishing the row refreshes without the need to
supply row addresses externally. 鈥楽elf Refresh鈥?further
simplifies the refresh requirements by eliminating the
need for address inputs and clock pulses entirely. An
automatic timer senses time periods when memory
accesses have ceased, and provides full refresh of all
rows of memory without any external assistance.
PIN CONNECTIONS
28-PIN DIP
28-PIN SK-DIP
28-PIN SOP
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
1
I/O
2
I/O
3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
R/W
A
13
A
8
A
9
A
11
OE/RFSH
A
10
CE
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
5P832-1
TOP VIEW
Figure 1. Pin Connections for DIP, SK-DIP,
and SOP Packages
1

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