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LH5P8129 Datasheet

  • LH5P8129

  • CMOS 1M (128K x 8) CS-Control Pseudo-Static RAM

  • 14頁

  • SHARP

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LH5P8129
FEATURES
鈥?/div>
131,072
脳
8 bit organization
鈥?/div>
Access times (MAX.): 60/80/100 ns
鈥?/div>
Cycle times (MIN.): 100/130/160 ns
鈥?/div>
Single +5 V power supply
鈥?/div>
Pin compatible with 1M standard SRAM
鈥?/div>
Power consumption:
Operating: 572/385/275 mW (MAX.)
Standby (TTL level): 5.5 mW (MAX.)
Standby (CMOS level): 1.1 mW (MAX.)
鈥?/div>
TTL compatible I/O
鈥?/div>
Available for auto-refresh and self-refresh
modes
鈥?/div>
512 refresh cycles/8 ms
鈥?/div>
Packages:
32-pin, 600-mil DIP
32-pin, 525-mil SOP
32-pin, 8
脳
20 mm
2
TSOP (Type I)
DESCRIPTION
The LH5P8129 is a 1M bit Pseudo-Static RAM
organized as 131,072
脳
8 bits. It is fabricated using
silicon-gate CMOS process technology.
A PSRAM uses on-chip refresh circuitry with a DRAM
memory cell for pseudo static operation which elimi-
nates external clock inputs, while considering the pinout
compatibility with industry standard SRAMs. The
advantage is the cost savings realized with the lower
cost PSRAM.
The LH5P8129 PSRAM has a built-in oscillator, which
makes it easy to refresh memories without external
clocks.
CMOS 1M (128K
脳
8)
CS-Control Pseudo-Static RAM
PIN CONNECTIONS
32-PIN DIP
32-PIN SOP
RFSH
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
CS
R/W
A
13
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
5P8129-1
TOP VIEW
Figure 1. Pin Connections for DIP and
SOP Packages
32-PIN TSOP (Type I)
TOP VIEW
A
11
A
9
A
8
A
13
R/W
CS
A
15
V
CC
RFSH
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
NOTE:
Reverse bend available on request.
5P8129-2
Figure 2. Pin Connections for TSOP Package
1

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