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Packages:
28-Pin, 300-mil DIP
28-Pin PLCC
FUNCTIONAL DESCRIPTION
The LH5481 and LH5491 are high-performance, asyn-
chronous First-In, First-Out (FIFO) memories organized
64 words deep by eight or nine bits wide. The eight-bit
LH5481 has an Output Enable (OE) function, which can
be used to force the eight data outputs (DO) to a high-im-
pedance state. The LH5491 has nine data outputs.
These FIFOs accept eight or nine-bit data at the Data
Inputs (DI). A Shift In (SI) signal writes the DI data into the
FIFO. A Shift Out (SO) signal shifts stored data to the Data
Outputs (DO). The Output Ready (OR) signal indicates
when valid data is present on the DO outputs.
If the FIFO is full and unable to accept more DI data,
Input Ready (IR) will not return HIGH, and SI pulses will
be ignored. If the FIFO is empty and unable to shift data
to the DO outputs, OR will not return HIGH, and SO
pulses will be ignored. The Almost-Full/Almost-Empty
(AFE) flag is asserted (HIGH) when the FIFO is almost-full
(56 words or more) or almost- empty (eight words or less).
Cascadable 64
脳
8 FIFO
Cascadable 64
脳
9 FIFO
The Half-Full (HF) flag is asserted (HIGH) when the FIFO
contains 32 words or more.
Reading and writing operations may be asynchronous,
allowing these FIFOs to be used as buffers between
digital machines of different operating frequencies. The
high speed makes these FIFOs ideal for high perform-
ance communication and controller applications.
PIN CONNECTIONS
28-PIN PDIP
AFE
HF
IR
SI
DI
0
DI
1
V
SS
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
NC/DI
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
MR
SO
OR
DO
0
DO
1
V
SS
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
OE/DO
8
5481-1D
TOP VIEW
Figure 1. Pin Connections for DIP Package
28-PIN PLCC
AFE
V
CC
MR
HF
IR
SO
SI
TOP VIEW
4
DI
0
DI
1
V
SS
DI
2
DI
3
DI
4
DI
5
5
6
7
8
9
10
11
3
2
1
28 27 26
25
24
23
22
21
20
19
OR
DO
0
DO
1
V
SS
DO
2
DO
3
DO
4
12 13 14 15 16 17 18
NC/DI
8
DO
6
DI
6
DI
7
OE/DO
8
DO
7
DO
5
5481-2D
Figure 2. Pin Connections for PLCC Package
1