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LH540205 Datasheet

  • LH540205

  • CMOS 8192 x 9 Asynchronous FIFO

  • 17頁(yè)

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LH540205
FEATURES
鈥?/div>
Fast Access Times: 20/25/35/50 ns
鈥?/div>
Fast-Fall-Through Time Architecture Based on
CMOS Dual-Port SRAM Technology
鈥?/div>
Input Port and Output Port Have Entirely
Independent Timing
鈥?/div>
Expandable in Width and Depth
鈥?/div>
Full, Half-Full, and Empty Status Flags
鈥?/div>
Data Retransmission Capability
鈥?/div>
TTL-Compatible I/O
鈥?/div>
Pin and Functionally Compatible with Am/IDT7205
鈥?/div>
Control Signals Assertive-LOW for Noise Immunity
鈥?/div>
Package: 28-Pin, 300-mil PDIP
CMOS 8192
脳
9 Asynchronous FIFO
Data words are read out from the LH540205鈥檚 output
port in precisely the same order that they were written in
at its input port; that is, according to a First-In, First Out
(FIFO) queue discipline. Since the addressing sequence
for a FIFO device鈥檚 memory is internally predefined, no
external addressing information is required for the opera-
tion of the LH540205 device.
Drop-in-replacement compatibility is maintained with
both larger sizes and smaller sizes of industry-standard
nine-bit asynchronous FIFOs. The only change is in the
number of internally-stored data words implied by the
states of the Full Flag and the Half-Full Flag.
The Retransmit (RT) control signal causes the internal
FIFO-memory-array read-address pointer to be set back
to zero, to point to the LH540205鈥檚 first physical memory
location, without affecting the internal FIFO-memory-
array write-address pointer. Thus, the Retransmit control
signal provides a mechanism whereby a block of data,
delimited by the zero physical address and the current
write-address-pointer value, may be read out
repeatedly
an arbitrary number of times. The only restrictions are that
neither the read-address pointer nor the write-address
pointer may 鈥榳rap around鈥?during this entire process, i.e.,
advance past physical location zero after traversing the
entire memory. The retransmit facility is not available
when an LH540205 is operating in a depth-expanded
configuration.
FUNCTIONAL DESCRIPTION
The LH540205 is a FIFO (First-In, First-Out) memory
device, based on fully-static CMOS dual-port SRAM tech-
nology, capable of storing up to 8192 nine-bit words. It
follows the industry-standard architecture and package
pinouts for nine-bit asynchronous FIFOs. Each nine-bit
LH540205 word may consist of a standard eight-bit byte,
together with a parity bit or a block-marking/framing bit.
The input and output ports operate entirely inde-
pendently of each other, unless the LH540205 becomes
either totally full or else totally empty. Data flow at a port
is initiated by asserting either of two asynchronous, as-
sertive-LOW control inputs: Write (W) for data entry at the
input port, or Read (R) for data retrieval at the output port.
Full, Half-Full, and Empty status flags monitor the
extent to which the internal memory has been filled. The
system may make use of these status outputs to avoid
the risk of data loss, which otherwise might occur either
by attempting to write additional words into an already-full
LH540205, or by attempting to read additional words from
an already-empty LH540205. When an LH540205 is
operating in a depth-cascaded configuration, the Half-Full
Flag is not available.
PIN CONNECTIONS
28-PIN PDIP
W
D
8
D
3
D
2
D
1
D
0
XI
FF
Q
0
Q
1
Q
2
Q
3
Q
8
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
D
4
D
5
D
6
D
7
FL/RT
RS
EF
XO/HF
Q
7
Q
6
Q
5
Q
4
R
540205-2D
TOP VIEW
Figure 1. Pin Connections for PDIP Packages
1

LH540205相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
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    256 x 36 x 2 Bidirectional FIFO
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    Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO
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    Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO
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    4K x 9 Parallel-to Serial FIFO
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    CMOS 512 X 9 FIFO
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    CMOS 512 X 9 FIFO
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    CMOS 512 x 9 FIFO
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    CMOS 1K X 9 FIFO
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    CMOS 2K X 9 FIFO
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    CMOS 4K X 9 FIFO
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    CMOS 512 X 9 FIFO
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  • 英文版
    CMOS 512 x 9 FIFO
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    CMOS 512 X 9 FIFO
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