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LH540203 Datasheet

  • LH540203

  • CMOS 2048 x 9 Asynchronous FIFO

  • 17頁

  • SHARP

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LH540203
FEATURES
鈥?/div>
Fast Access Times: 15/20/25/35/50 ns
鈥?/div>
Fast-Fall-Through Time Architecture Based on
CMOS Dual-Port SRAM Technology
鈥?/div>
Input Port and Output Port Have Entirely
Independent Timing
鈥?/div>
Expandable in Width and Depth
鈥?/div>
Full, Half-Full, and Empty Status Flags
鈥?/div>
Data Retransmission Capability
鈥?/div>
TTL-Compatible I/O
鈥?/div>
Pin and Functionally Compatible with Sharp LH5498
and with Am/IDT/MS7203
鈥?/div>
Control Signals Assertive-LOW for Noise Immunity
鈥?/div>
Packages:
28-Pin, 300-mil PDIP
28-Pin, 300-mil SOJ *
32-Pin PLCC
CMOS 2048
脳
9 Asynchronous FIFO
FUNCTIONAL DESCRIPTION
The LH540203 is a FIFO (First-In, First-Out) memory
device, based on fully-static CMOS dual-port SRAM tech-
nology, capable of storing up to 2048 nine-bit words. It
follows the industry-standard architecture and package
pinouts for nine-bit asynchronous FIFOs. Each nine-bit
LH540203 word may consist of a standard eight-bit byte,
together with a parity bit or a block-marking/framing bit.
The input and output ports operate entirely inde-
pendently of each other, unless the LH540203 becomes
either totally full or else totally empty. Data flow at a port
is initiated by asserting either of two asynchronous, as-
sertive-LOW control inputs: Write (W) for data entry at the
input port, or Read (R) for data retrieval at the output port.
Full, Half-Full, and Empty status flags monitor the
extent to which the internal memory has been filled. The
system may make use of these status outputs to avoid
the risk of data loss, which otherwise might occur either
by attempting to write additional words into an already-full
LH540203, or by attempting to read additional words from
an already-empty LH540203. When an LH540203 is
operating in a depth-cascaded configuration, the Half-Full
Flag is not available.
PIN CONNECTIONS
NC
*
28-PIN PDIP
28-PIN SOJ
*
D
3
D
8
D
4
W
D
8
D
3
D
2
D
1
D
0
XI
FF
Q
0
Q
1
Q
2
Q
3
Q
8
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
D
4
D
5
D
6
D
7
FL/RT
RS
EF
XO/HF
Q
7
Q
6
Q
5
Q
4
R
540203-2D
4
D
2
D
1
D
0
XI
FF
Q
0
Q
1
NC
Q
2
5
6
7
8
9
10
11
12
13
3
2
1
32 31 30
29
28
27
26
25
24
23
22
21
D
6
D
7
NC
FL/RT
RS
EF
XO/HF
Q
7
Q
6
14 15 16 17 18 19 20
NC
*
Q
3
V
SS
Q
8
R
Q
4
NOTE:
*
= No external electrical connections are allowed.
540203-3D
Figure 1. Pin Connections for PDIP and
SOJ * Packages
Figure 2. Pin Connections for PLCC Package
* This is a final data sheet; except that all references to the SOJ package have Advance Information status.
Q
5
D
5
W
TOP VIEW
32-PIN PLCC
V
CC
TOP VIEW
1

LH540203相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    256 x 36 x 2 Bidirectional FIFO
    SHARP
  • 英文版
    5 mm T1 3/4 LED, Non Diffused Super-Bright, Hyper-Red GaAIAs...
    INFINEON
  • 英文版
    5 mm T1 3/4 LED, Non Diffused Super-Bright, Hyper-Red GaAIAs...
    SIEMENS [S...
  • 英文版
    5 mm T1 3/4 LED, Diffused Super-Bright, Hyper-Red GaAIAs-LED
    INFINEON
  • 英文版
    5 mm T1 3/4 LED, Diffused Super-Bright, Hyper-Red GaAIAs-LED
    SIEMENS [S...
  • 英文版
    Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO
    SHARP
  • 英文版
    Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO
    SHARP [Sha...
  • 英文版
    Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO
    SHARP
  • 英文版
    Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO
    SHARP [Sha...
  • 英文版
    4K x 9 Parallel-to Serial FIFO
    SHARP
  • 英文版
    CMOS 512 X 9 FIFO
    SHARP
  • 英文版
    CMOS 512 X 9 FIFO
    SHARP [Sha...
  • 英文版
    CMOS 512 x 9 FIFO
    SHARP [Sha...
  • 英文版
    CMOS 1K X 9 FIFO
    SHARP
  • 英文版
    CMOS 2K X 9 FIFO
    SHARP
  • 英文版
    CMOS 4K X 9 FIFO
    SHARP
  • 英文版
    CMOS 512 X 9 FIFO
    SHARP
  • 英文版
    CMOS 512 x 9 FIFO
    SHARP [Sha...
  • 英文版
    CMOS 512 X 9 FIFO
    SHARP [Sha...
  • 英文版
    CMOS 512 X 9 FIFO
    SHARP

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