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LH5332600 Datasheet

  • LH5332600

  • CMOS 32M (4M x 8/2M x 16) MROM

  • 8頁

  • SHARP

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LH5332600
FEATURES
鈥?/div>
4,194,304
脳
8 bit organization
(Byte mode: BYTE = V
IL
)
2,097,152
脳
16 bit organization
(Word mode: BYTE = V
IH
)
鈥?/div>
Access time: 100 ns (MAX.)
鈥?/div>
Supply current:
鈥?Operating: 100 mA (MAX.)
鈥?Standby: 100
碌A(chǔ)
(MAX.)
鈥?/div>
TTL compatible I/O
鈥?/div>
Three-state output
鈥?/div>
Single +5 V power supply
鈥?/div>
Static operation
鈥?/div>
Packages:
44-pin, 600-mil SOP
48-pin, 12 mm
脳
18 mm
2
TSOP (Type I)
鈥?/div>
Others:
鈥?Non programmable
鈥?Not designed or rated as radiation
hardened
鈥?CMOS process (P type silicon
substrate)
DESCRIPTION
The LH5332600 is a 32M-bit mask-programmable
ROM organized as 4,194,304
脳
8 bits (Byte mode) or
2,097,152
脳
16 bits (Word mode) that can be selected
by a BYTE input pin. It is fabricated using silicon-gate
CMOS process technology.
CMOS 32M (4M
脳
8/2M
脳
16) MROM
PIN CONNECTIONS
44-PIN SOP
TOP VIEW
NC
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
GND
OE
D
0
D
8
D
1
D
9
D
2
D
10
D
3
D
11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
20
A
19
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
BYTE
GND
D
15
/A
-1
(NOTE)
D
7
D
14
D
6
D
13
D
5
D
12
D
4
V
CC
NOTE:
The D
15
/A
-1
pin becomes LSB address input (A
-1
)
when the BYTE pin is set to be LOW in byte mode and
data output (D
15
) when set to be HIGH in word mode.
5332600N-1
Figure 1. SOP Pin Connections
1

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