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LH5324C00 Datasheet

  • LH5324C00

  • CMOS 24M (1.5M x 16) MROM

  • 6頁

  • SHARP

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LH5324C00
FEATURES
鈥?/div>
1,572,864
脳
16 bit organization
鈥?/div>
Access time: 120 ns (MAX.)
鈥?/div>
Supply current:
鈥?Operating: 80 mA (MAX.)
鈥?Standby: 100
碌A(chǔ)
(MAX.)
鈥?/div>
TTL compatible I/O
鈥?/div>
Three-state output
鈥?/div>
Single +5 V Power supply
鈥?/div>
Static operation
鈥?/div>
When the address input at both A
19
and
A
20
is high level, outputs become high
impedance irrespective of CE or OE.
鈥?/div>
Package:
42-pin, 600-mil DIP
鈥?/div>
Others:
鈥?Non programmable
鈥?Not designed or rated as radiation
hardened
鈥?CMOS process (P type silicon
substrate)
DESCRIPTION
The LH5324C00 is a 24M-bit mask-programmable
ROM organized as 1,572,864
脳
16 bits. It is fabricated
using silicon-gate CMOS process technology.
42-PIN DIP
CMOS 24M (1.5M
脳
16) MROM
PIN CONNECTIONS
TOP VIEW
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
GND
OE
D
0
D
8
D
1
D
9
D
2
D
10
D
3
D
11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
A
19
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
20
GND
D
15
D
7
D
14
D
6
D
13
D
5
D
12
D
4
V
CC
5324C00-1
Figure 1. Pin Connections
1

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