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LH532000B Datasheet

  • LH532000B

  • CMOS 2M (256K x 8/128K x 16) MROM

  • 7頁

  • SHARP

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LH532000B
FEATURES
鈥?/div>
262,144 words
脳
8 bit organization
(Byte mode)
131,072 words
脳
16 bit organization
(Word mode)
鈥?/div>
BYTE input pin selects bit configuration
鈥?/div>
Access times: 120/150 ns (MAX.)
鈥?/div>
Low-power consumption:
Operating: 275 mW (MAX.)
Standby: 550
碌W
(MAX.)
鈥?/div>
Programmable OE/OE and OE
1
/OE
1
/DC
鈥?/div>
Static operation
鈥?/div>
TTL compatible I/O
鈥?/div>
Three-state outputs
鈥?/div>
Single +5 V power supply
鈥?/div>
Packages:
40-pin, 600-mil DIP
40-pin, 525-mil SOP
48-pin, 12
脳
18 mm
2
TSOP (Type I)
鈥?脳16
word-wide pinout
DESCRIPTION
The LH532000B is a 2M-bit mask-programmable
ROM with two programmable memory organizations,
byte and word modes. It is fabricated using silicon-gate
CMOS process technology.
CMOS 2M (256K
脳
8/128K
脳
16) MROM
PIN CONNECTIONS
40-PIN DIP
40-PIN SOP
TOP VIEW
OE
1
/OE
1
/DC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
GND
OE/OE
D
0
D
8
D
1
D
9
D
2
D
10
D
3
D
11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
48
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
BYTE
GND
D
15
/A
-1
(LSB)
D
7
D
14
D
6
D
13
D
5
D
12
D
4
V
CC
532000B-1
Figure 1. Pin Connections for DIP and
SOP Packages
1

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