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LH531V00 Datasheet

  • LH531V00

  • CMOS 1M (128K x 8) MROM

  • 6頁(yè)

  • SHARP

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LH531V00
FEATURES
鈥?/div>
131,072 words
脳
8 bit organization
鈥?/div>
Access time: 100 ns (MAX.)
鈥?/div>
Power consumption:
Operating: 275 mW (MAX.)
Standby: 550
碌W
(MAX.)
鈥?/div>
Mask-programmable OE
1
/OE
1
/DC
鈥?/div>
Fully-static operation
鈥?/div>
TTL-compatible I/O
鈥?/div>
Three-state outputs
鈥?/div>
Single +5 V power supply
鈥?/div>
Packages:
32-pin, 600-mil DIP
32-pin, 525-mil SOP
32-pin, 8
脳
20 mm
2
TSOP (Type I)
DESCRIPTION
The LH531V00 is a 1M-bit mask-programmable ROM
organized as 131,072
脳
8 bits. It is fabricated using
silicon-gate CMOS process technology.
32-PIN DIP
32-PIN SOP
OE
1
/OE
1
/DC
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
0
D
1
D
2
GND
CMOS 1M (128K
脳
8) MROM
PIN CONNECTIONS
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
NC
NC
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE
D
7
D
6
D
5
D
4
D
3
531V00-1
Figure 1. Pin Connections for DIP and
SOP Packages
32-PIN TSOP (Type I)
TOP VIEW
A
11
A
9
A
8
A
13
A
14
NC
NC
V
CC
OE
1
/OE
1
/DC
A
16
A
15
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
10
CE
D
7
D
6
D
5
D
4
D
3
GND
D
2
D
1
D
0
A
0
A
1
A
2
A
3
531V00-2
Figure 2. Pin Connections for TSOP Package
1

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