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LH531024 Datasheet

  • LH531024

  • CMOS 1M (64K x 16) MROM

  • 7頁

  • SHARP

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LH531024
FEATURES
鈥?/div>
65,536 words
脳
16 bit organization
鈥?/div>
Access time: 100 ns (MAX.)
鈥?/div>
Power consumption:
Operating: 412.5 mW (MAX.)
Standby: 550
碌W
(MAX.)
鈥?/div>
Static operation
鈥?/div>
TTL compatible I/O
鈥?/div>
Three-state outputs
鈥?/div>
Single +5 V power supply
鈥?/div>
JEDEC standard EPROM pinout (DIP)
鈥?/div>
Packages:
40-pin, 600-mil DIP
40-pin, 525-mil SOP
44-pin, 650-mil QFJ (PLCC)
DESCRIPTION
The LH531024 is a mask-programmable ROM
organized as 65,536
脳
16 bits. It is fabricated using
silicon-gate CMOS process technology.
NC
CE
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
GND
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
OE
40-PIN DIP
40-PIN SOP
CMOS 1M (64K
脳
16) MROM
PIN CONNECTIONS
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
CC
NC
NC
A
15
A
14
A
13
A
12
A
11
A
10
A
9
GND
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
531024-1
Figure 1. Pin Connections for DIP and
SOP Packages
44-PIN PLCC
TOP VIEW
D
12
D
11
D
10
D
9
D
8
GND
NC
D
7
D
6
D
5
D
4
7
8
9
10
11
12
13
14
15
16
D
13
D
14
D
15
CE
NC
NC
V
CC
NC
NC
A
15
A
14
6 5 4 3 2 1 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
A
13
A
12
A
11
A
10
A
9
GND
NC
A
8
A
7
A
6
A
5
29
17
18 19 20 21 22 23 24 25 26 27 28
D
3
D
2
D
1
D
0
OE
NC
A
0
A
1
A
2
A
3
A
4
531024-2
Figure 2. Pin Connections for QFJ
(PLCC) Package
1

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