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LH530800A Datasheet

  • LH530800A

  • CMOS 1M (128K x 8) MROM

  • 64.67KB

  • 6頁

  • SHARP

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LH530800A
FEATURES
鈥?/div>
131,072 words
脳
8 bit organization
鈥?/div>
Access time: 150 ns (MAX.)
鈥?/div>
Power consumption:
Operating: 192.5 mW (MAX.)
Standby: 550
碌W
(MAX.)
鈥?/div>
Static operation
鈥?/div>
TTL compatible I/O
鈥?/div>
Three-state outputs
鈥?/div>
Single +5 V power supply
鈥?/div>
Packages:
32-pin, 600-mil DIP
32-pin, 525-mil SOP
32-pin, 450-mil QFJ (PLCC)
鈥?/div>
JEDEC standard EPROM pinout (DIP)
DESCRIPTION
The LH530800A is a mask-programmable ROM
organized as 131,072
脳
8 bits (1,048,576 bits). It is fab-
ricated using silicon-gate CMOS process technology.
32-PIN DIP
32-PIN SOP
CMOS 1M (128K
脳
8) MROM
PIN CONNECTIONS
TOP VIEW
NC
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
0
D
1
D
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
NC
NC
A
14
A
13
A
8
A
9
A
11
OE/OE
A
10
CE
D
7
D
6
D
5
D
4
D
3
530800A-1
Figure 1. Pin Connections for DIP and
SOP Packages
32-PIN QFJ
TOP VIEW
V
CC
A
12
A
15
A
16
NC
NC
4
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
0
5
6
7
8
9
10
11
12
13
3
2
1
32 31 30
29
28
27
26
25
24
23
22
21
A
14
A
13
A
8
A
9
A
11
OE/OE
A
10
CE
D
7
14 15 16 17 18 19 20
D
1
GND
D
2
D
3
D
4
D
5
D
6
NC
530800A-7
Figure 2. Pin Connections for QFJ
(PLCC) Package
1

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