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LH52256CH Datasheet

  • LH52256CH

  • CMOS 256K (32K x 8) Static RAM

  • 99.81KB

  • 11頁(yè)

  • SHARP

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LH52256C/CH
FEATURES
鈥?/div>
32,768
脳
8 bit organization
鈥?/div>
Access time: 70 ns (MAX.)
鈥?/div>
Supply current:
Operating: 45 mA (MAX.)
10 mA (MAX.) (t
RC
, t
WC
= 1
碌s)
Standby: 40
碌A(chǔ)
(MAX.)
鈥?/div>
Data retention current: 1.0
碌A(chǔ)
(MAX.)
(V
CCDR
= 3 V, T
A
= 25擄C)
鈥?/div>
Wide operating voltage range:
4.5 V
鹵
5.5 V
鈥?/div>
Operating temperature:
Commerical temperature 0擄C to +70擄C
Industrial temperature -40擄 to +85擄C
鈥?/div>
Fully-static operation
鈥?/div>
Three-state outputs
鈥?/div>
Not designed or rated as radiation
hardened
鈥?/div>
Package:
28-pin, 600-mil DIP
28-pin, 450-mil SOP
28-pin, 300-mil SK-DIP
28-pin, 8
脳
3 mm
2
TSOP (Type I)
鈥?/div>
N-type bulk silicon
DESCRIPTION
The LH52256C is a Static RAM organized as
32,768
脳
8 bits which provides low-power standby
mode. It is fabricated using silicon-gate CMOS process
technology.
CMOS 256K (32K
脳
8) Static RAM
PIN CONNECTIONS
28-PIN DIP
28-PIN SK-DIP
28-PIN SOP
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
1
I/O
2
I/O
3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
52256C-1
TOP VIEW
Figure 1. Pin Connections
28-PIN TSOP (Type I)
OE
A
11
A
9
A
8
A
13
WE
V
CC
A
14
A
12
A
7
A
6
A
5
A
4
A
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
10
CE
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
GND
I/O
3
I/O
2
I/O
1
A
0
A
1
A
2
NOTE:
Reverse bend available on request.
52256C-8
Figure 2. TSOP (Type I) Pin Connections
1

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