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LH521028 Datasheet

  • LH521028

  • CMOS 64K x 18 Static RAM

  • 156.26KB

  • 15頁

  • SHARP

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LH521028
FEATURES
鈥?/div>
Fast Access Times: 17/20/25/35 ns
鈥?/div>
Wide Word (18-Bits) for:
鈥?Improved Performance
鈥?Reduced Component Count
鈥?Nine-bit Byte for Parity
鈥?/div>
Transparent Address Latch
鈥?/div>
Reduced Loading on Address Bus
鈥?/div>
Low-Power Stand-by Mode when
Deselected
鈥?/div>
TTL Compatible I/O
鈥?/div>
5 V
鹵
10% Supply
鈥?/div>
2 V Data Retention
鈥?/div>
JEDEC Standard Pinout
鈥?/div>
Package: 52-Pin PLCC
52-PIN PLCC
CMOS 64K
脳
18 Static RAM
operations on the high and the low bytes. The Address
Latches are transparent when ALE is HIGH (for applica-
tions not requiring a latch), and are latched when ALE is
LOW. The Address Latches and the wide word help to
eliminate the need for external Address busbuffers and/or
latches.
Write cycles occur when Chip Enable (E), S
H
and/or
S
L
, and Write Enable (W) are LOW. The Byte-select
signals can be used for Byte-write operations by disabling
the other byte during the Write operation. Data is trans-
ferred from the DQ pins to the memory location specified
by the 16 address lines. The proper use of the Output
Enable control (G) can prevent bus contention.
When E and either S
H
or S
L
are LOW and W is HIGH,
a static Read will occur at the memory location specified
by the address lines. G must be brought LOW to enable
the outputs. Since the device is fully static in operation,
new Read cycles can be performed by simply changing
the address with ALE HIGH.
PIN CONNECTIONS
TOP VIEW
ALE
V
CC
V
SS
A
15
A
14
A
0
S
L
A
13
46
45
44
43
42
41
40
39
38
37
36
35
34
DQ
8
DQ
7
DQ
6
V
CC
V
SS
DQ
5
DQ
4
DQ
3
DQ
2
V
SS
V
CC
DQ
1
DQ
0
S
H
A
1
W
The LH521028 is a high-speed 1,179,648-bit CMOS
SRAM organized as 64K
脳
18. A fast, efficient design is
obtained with a CMOS periphery and a matrix con-
structed with polysilicon load memory cells. The
LH521028 is available in a compact 52-Pin PLCC, which
along with the six pairs of supply terminals, provide for
reliable operation.
The control signals include Write Enable (W), Chip
Enable (E), High and Low Byte Select (S
L
and S
H
), Output
Enable (G) and Address Latch Enable (ALE). The wide
word provides for reduced component count, improved
density, reduced Address bus loading and improved per-
formance. The wide word also allows for byte-parity with
no additional RAM required.
This RAM is fully static in operation. The Chip Enable
(E) control permits Read and Write operations when
active (LOW) or places the RAM in a low-power standby
mode when inactive (HIGH).The Byte-select controls, S
H
and S
L
, are also used to enable or disable Read and Write
DQ
9
DQ
10
V
CC
V
SS
DQ
11
DQ
12
DQ
13
DQ
14
V
SS
V
CC
DQ
15
DQ
16
DQ
17
7
8
9
10
11
12
13
14
15
16
17
18
19
6 5
E
4 3 2 1 52 51 50 49 48 47
20
21 22 23 24 25 26 27 28 29 30 31 32 33
G
FUNCTIONAL DESCRIPTION
A
11
V
SS
V
CC
A
10
A
12
521028-1D
A
4
A
2
A
3
A
5
A
6
A
8
Figure 1. Pin Connections for PLCC Package
A
7
A
9
4-211

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