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LH28F040SUTD-Z4 Datasheet

  • LH28F040SUTD-Z4

  • 4M (512K 】 8) Flash Memory

  • 32頁(yè)

  • SHARP

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LH28F040SUTD-Z4
FEATURES
40-PIN TSOP
4M (512K 脳 8) Flash Memory
TOP VIEW
鈥?/div>
512K 脳 8 Bit Configuration
鈥?/div>
5 V Write/Erase Operation (5 V V
PP
, 3.3 V
CC
)
鈥?V
CC
for Write/Erase at as low as 2.9 V
鈥?/div>
Min. 2.7 V Read Capability
鈥?190 ns Maximum Access Time
(V
CC
= 2.7 V)
NC1
NC1
A
11
A
9
A
8
A
13
A
14
A
17
WE
V
CC
V
PP
A
16
A
15
A
12
A
7
A
6
A
5
A
4
NC2
NC2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
OE
NC
A
10
BE
1
BE
0
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
GND
DQ
2
DQ
1
DQ
0
A
0
A
1
A
2
A
3
NC
28F040SUZ4-1
鈥?/div>
2 Banks Enable the Simultaneous
Read/Write/Erase Operation
鈥?/div>
32 Independently Lockable Blocks (16K)
鈥?/div>
100,000 Erase Cycles per Block
鈥?/div>
Automated Byte Write/Block Erase
鈥?Command User Interface
鈥?Status Register
鈥?/div>
System Performance Enhancement
鈥?Erase Suspend for Read
鈥?Two-Byte Write
鈥?Bank Erase
鈥?/div>
Data Protection
鈥?Hardware Erase/Write Lockout during
Power Transitions
鈥?Software Erase/Write Lockout
Figure 1. TSOP Configuration
鈥?/div>
Independently Lockable for Write/Erase
on Each Block (Lock Block and Protect
Set/Reset)
鈥?/div>
20 碌A(chǔ) (Maximum) I
CC
in CMOS Standby
鈥?/div>
State-of-the-Art 0.55 碌m ETOX鈩?/div>
Flash Technology
鈥?/div>
40-Pin, 1.2 mm 脳 10 mm 脳 20 mm TSOP
(Type I) Package
1

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