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LH28F008SC Datasheet

  • LH28F008SC

  • 8M (1M 】 8) Flash Memory

  • 38頁(yè)

  • SHARP

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LH28F008SC
FEATURES
42-PIN CSP
8M (1M 脳 8) Flash Memory
TOP VIEW
鈥?/div>
High-Density Symmetrically-Blocked
Architecture
鈥?Sixteen 64K Erasable Blocks
1
A
B
C
D
E
F
A
5
A
4
A
6
A
3
A
2
A
1
2
A
8
A
7
A
9
DQ
1
A
0
DQ
0
3
A
11
A
10
RP
NC
DQ
3
DQ
2
4
V
PP
V
CC
CE
V
CC
GND
GND
5
A
12
A
13
A
14
DQ
4
DQ
6
DQ
5
6
A
15
NC
A
16
DQ
7
OE
RY/BY
7
A
17
A
18
A
19
NC
NC
WE
鈥?/div>
High-Performance
鈥?85 ns Read Access Time
鈥?/div>
Enhanced Automated Suspend Options
鈥?Byte Write Suspend to Read
鈥?Block Erase Suspend to Byte Write
鈥?Block Erase Suspend to Read
鈥?/div>
Enhanced Data Protection Features
鈥?Absolute Protection with V
PP
= GND
鈥?Flexible Block Locking
鈥?Block Erase/Byte Write Lockout during
Power Transitions
28F008SC-20
Figure 1. CSP 42-Pin Configuration
40-PIN TSOP
TOP VIEW
鈥?/div>
Extended Cycling Capability
鈥?100,000 Block Erase Cycles
鈥?1.6 Million Block Erase Cycles/Chip
鈥?/div>
Low Power Management
鈥?Deep Power-Down Mode
鈥?Automatic Power Saving Mode Decreases
I
CC
in Static Mode
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
CE
V
CC
V
PP
RP
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
NC
WE
OE
RY/BY
DQ
7
DQ
6
DQ
5
DQ
4
V
CC
GND
GND
DQ
3
DQ
2
DQ
1
DQ
0
A
0
A
1
A
2
A
3
鈥?/div>
Automated Byte Write and Block Erase
鈥?Command User Interface
鈥?Status Register
鈥?/div>
SmartVoltage Technology
鈥?3.3 V or 5 V V
CC
鈥?3.3 V, 5 V, or 12 V V
PP
鈥?/div>
SRAM - Compatible Write Interface
鈥?/div>
ETOX鈩?V Nonvolatile Flash Technology
鈥?/div>
Industry - Standard Packaging
鈥?42-Pin, .67 mm 脳 8 mm
2
CSP Package
鈥?40-Pin, 1.2 mm 脳 10 mm 脳 20 mm
TSOP (Type I) Package
鈥?44-Pin, 600-mil, SOP Package
28F008SC-1
Figure 2. TSOP 40-Pin Configuration
1

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