鈥?/div>
Automated Byte Write/Block Erase
鈥?Command User Interface
鈥?Status Register
鈥?RY
聽
/BY
聽 祿
Status Output
祿
28F004SU-Z9-1
Figure 1. CSP Configuration
INTRODUCTION
Sharp鈥檚 LH28F004SU 4M Flash Memory is a revolu-
tionary architecture which enables the design of truly
mobile, high performance, personal computing and
communication products. With innovative capabilities,
3.3 V low power operation and very high read/write
performance, the LH28F004SU is also the ideal choice
for designing embedded mass storage flash memory
systems.
The LH28F004SU鈥檚 independently lockable 32 sym-
metrical blocked architecture (16K each) extended
cycling, low power operation, very fast write and read
performance and selective block locking provide a highly
flexible memory component suitable for cellular phone,
facsimile, game, PC, printer and handy terminal. The
LH28F004SU鈥檚 5.0 V/3.3 V power supply operation
enables the design of memory cards which can be read
in 3.3 V system and written in 5.0 V/3.3 V systems. Its
x8 architecture allows the optimization of memory to
processor interface. The flexible block locking option
enables bundling of executable application software in
a Resident Flash Array or memory card. Manufactured
on Sharp鈥檚 0.45 碌m ETOX鈩?process technology, the
LH28F004SU is the most cost-effective, high-density
3.3 V flash memory.
鈥?/div>
System Performance Enhancement
鈥?Erase Suspend For Read
鈥?Two-Byte Write
鈥?Full Chip Erase
鈥?/div>
Data Protection
鈥?Hardware Erase/Write Lockout During
Power Transitions
鈥?Software Erase/Write Lockout
鈥?/div>
Independently Lockable For Write/Erase
On Each Block (Lock Block and Protect
Set/Reset)
鈥?/div>
4 碌A(chǔ) (Typ.) I
CC
In CMOS Standby
鈥?/div>
0.2 碌A(chǔ) (Typ.) Deep Power-Down
鈥?/div>
State-of-the-Art 0.45 碌m ETOX鈩?/div>
Flash Technology
鈥?/div>
Extended Temperature Operation
鈥?-20擄C to +85擄C (Read)
鈥?+15擄C to +35擄C (Write/Erase)
鈥?/div>
42-pin, 0.67 mm 脳 8 mm 脳 8 mm
CSP Package
1
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