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LFX500B-4F900C Datasheet

  • LFX500B-4F900C

  • The ispXPGA architecture

  • 89頁

  • LATTICE   LATTICE

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ispXPGA Family
TM
March 2003
Preliminary Data Sheet
鈻?/div>
Non-volatile, In鏗乶itely Recon鏗乬urable
鈥?Instant-on - Powers up in microseconds via
on-chip E
2
CMOS
廬
based memory
鈥?No external con鏗乬uration memory
鈥?Excellent design security, no bit stream to intercept
鈥?Recon鏗乬ure SRAM based logic in milliseconds
鈻?/div>
Eight sysCLOCK鈩?Phase Locked Loops
(PLLs) for Clock Management
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
True PLL technology
10MHz to 320MHz operation
Clock multiplication and division
Phase adjustment
Shift clocks in 250ps steps
鈻?/div>
High Logic Density for System-level
Integration
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
139K to 1.25M system gates
160 to 496 I/O
1.8V, 2.5V, and 3.3V V
CC
operation
Up to 414Kb sysMEM鈩?embedded memory
鈻?/div>
sysIO鈩?for High System Performance
鈻?/div>
High Performance Programmable Function
Unit (PFU)
鈥?Four LUT-4 per PFU supports wide and narrow
functions
鈥?Dual
鏗俰p-鏗俹ps
per LUT-4 for extensive pipelining
鈥?Dedicated logic for adders, multipliers, multiplex-
ers, and counters
鈥?High speed memory support through SSTL and
HSTL
鈥?Advanced buses supported through PCI, GTL+,
LVDS, BLVDS, and LVPECL
鈥?Standard logic supported through LVTTL,
LVCMOS 3.3, 2.5, and 1.8
鈥?Programmable drive strength for series termination
鈥?Programmable bus maintenance
鈻?/div>
sysHSI鈩?Capability for Ultra Fast Serial
Communications
鈥?Up to 850Mbps performance
鈥?Up to 20 channels per device
鈥?Built in Clock Data Recovery (CDR) and
Serialization and De-serialization (SERDES)
鈻?/div>
Variable-Length Interconnect Routing
Technology
鈥?Optimum speed, power, and
鏗俥xibility
for logic
interconnections
鈻?/div>
Flexible Memory Resources
鈻?/div>
Flexible Programming, Recon鏗乬uration,
and Testing
鈥?IEEE 1532 and 1149.1 compliant
鈥?Microprocessor con鏗乬uration interface
鈥?Program E
2
CMOS while operating from SRAM
鈥?Multiple sysMEM Embedded RAM Blocks
鈥?Single port, Dual port, and FIFO operation
鈥?64-bit distributed memory in each PFU
鈥?Single port, Double port, FIFO, and Shift
Register operation
Table 1. ispXPGA Family Selection Guide
ispXPGA 125
System Gates
PFUs
LUT-4s
Logic FFs
sysMEM Memory
Distributed Memory
EBR
sysHSI Channels
User I/O
Packaging
139K
484
1936
3.8K
92K
30K
20
4
160/176
256 fpBGA
516 fpBGA
1
ispXPGA 200
210K
676
2704
5.4K
111K
43K
24
8
160/208
256 fpBGA
516 fpBGA
1
ispXPGA 500
476K
1764
7056
14.1K
184K
112K
40
12
336
516 fpBGA
1
900 fpBGA
1. Thermally enhanced package.
ispXPGA 1200
1.25M
3844
15376
30.7K
414K
246K
90
20
496
680 fpSBGA
1
900 fpBGA
Note: LFX1200B/C is preliminary, LFX125/200/500B/C information is advanced.
漏 2003 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The speci鏗乧ations and information herein are subject to change without notice.
www.latticesemi.com
1
xpga_04

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