Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifiers
LF198/LF298/LF398
DESCRIPTION
The LF198/LF298/LF398 are monolithic sample-and-hold circuits
which utilize high-voltage ion-implant JFET technology to obtain
ultra-high DC accuracy with fast acquisition of signal and low droop
rate. Operating as a unity gain follower, DC gain accuracy is 0.002%
typical and acquisition time is as low as 6碌s to 0.01%. A bipolar
input stage is used to achieve low offset voltage and wide
bandwidth. Input offset adjust is accomplished with a single pin and
does not degrade input offset drift. The wide bandwidth allows the
LF198 to be included inside the feedback loop of 1MHz op amps
without having stability problems. Input impedance of 10
10
鈩?/div>
allows
high source impedances to be used without degrading accuracy.
P-channel junction FETs are combined with bipolar devices in the
output amplifier to give droop rates as low as 5mV/min with a 1碌F
hold capacitor. The JFETs have much lower noise than MOS
devices used in previous designs and do not exhibit high
temperature instabilities. The overall design guarantees no
feedthrough from input to output in the hold mode even for input
signals equal to the supply voltages.
Logic inputs are fully differential with low input current, allowing
direct connection to TTL, PMOS, and CMOS; differential threshold is
1.4V. The LF198/LF298/LF398 will operate from
鹵5V
to
鹵18V
supplies. They are available in 8-pin plastic DIP, 8-pin Cerdip, and
14-pin plastic SO packages.
PIN CONFIGURATIONS
FE, N Packages
1
2
3
4
TOP VIEW
8
7
6
5
V+
OFFSET VOLTAGE
INPUT
V鈥?/div>
LOGIC
LOGIC REFERENCE
C
h
OUTPUT
D
1
Package
INPUT
1
NC
2
V鈥?/div>
3
NC
4
NC
5
NC
6
OUTPUT
7
TOP VIEW
14
V
OS
Adj
13
NC
12
V+
11
LOGIC
10
LOGIC REF
9
8
NC
C
h
FEATURES
鈥?/div>
Operates from
鹵5V
to
鹵18V
supplies
鈥?/div>
Less than 10碌s acquisition time
鈥?/div>
TTL, PMOS, CMOS compatible logic input
鈥?/div>
0.5mV typical hold step at CH=0.01碌F
鈥?/div>
Low input offset
鈥?/div>
0.002% gain accuracy
鈥?/div>
Low output noise in hold mode
鈥?/div>
Input characteristics do not change during hold mode
鈥?/div>
High supply rejection ratio in sample or hold
鈥?/div>
Wide bandwidth
ORDERING INFORMATION
DESCRIPTION
8-Pin Ceramic Dual In-Line Package (CERDIP)
14-Pin Plastic Small Outline (SO) Package
8-Pin Ceramic Dual In-Line Package (CERDIP)
8-Pin Plastic Dual In-Line Package (DIP)
8-Pin Ceramic Dual In-Line Package (CERDIP)
8-Pin Plastic Dual In-Line Package (DIP)
NOTE:
1. SO and non-standard pinouts.
APPLICATION
鈥?/div>
The LF198/LF298/LF398 are ideally suited for a wide variety of
sample-and-hold applications, including data acquisition,
analog-to-digital conversion, synchronous demodulation, and
automatic test setup
TEMPERATURE RANGE
-55擄C to +125擄C
0 to +70擄C
0 to +70擄C
0 to +70擄C
-25擄C to +85擄C
-25擄C to +85擄C
ORDER CODE
LF198FE
LF398D
LF398FE
LF398N
LF298FE
LF298N
DWG #
0580A
0175D
0580A
0404B
0580A
0404B
August 31, 1994
879
853-0135 13721
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