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LDH374A Datasheet

  • LDH374A

  • 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

  • 300.58KB

  • 13頁

  • TI

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SN74LVCH16374A
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS565L 鈥?MARCH 1996 鈥?REVISED SEPTEMBER 2003
D
D
D
D
D
D
D
D
D
D
D
Member of the Texas Instruments
Widebus
錚?/div>
Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t
pd
of 4.5 ns at 3.3 V
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25擄C
Typical V
OHV
(Output V
OH
Undershoot)
>2 V at V
CC
= 3.3 V, T
A
= 25擄C
I
off
Supports Partial-Power-Down Mode
Operation
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input and Output Voltages
With 3.3-V V
CC
)
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
鈥?2000-V Human-Body Model (A114-A)
鈥?1000-V Charged-Device Model (C101)
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
description/ordering information
This 16-bit edge-triggered D-type flip-flop is
designed for 1.65-V to 3.6-V V
CC
operation.
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
V
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1CLK
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V
CC
2D5
2D6
GND
2D7
2D8
2CLK
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
ORDERING INFORMATION
TA
SSOP 鈥?DL
鈥?0擄C 85擄C
鈥?0 C to 85 C
TSSOP 鈥?DGG
TVSOP 鈥?DGV
VFBGA 鈥?GQL
VFBGA 鈥?ZQL (Pb-free)
PACKAGE鈥?/div>
Tube
Tape and reel
Tape and reel
Tape and reel
Tape and reel
ORDERABLE
PART NUMBER
SN74LVCH16374ADL
SN74LVCH16374ADLR
SN74LVCH16374ADGGR
SN74LVCH16374ADGVR
SN74LVCH16374AGQLR
SN74LVCH16374AZQLR
TOP-SIDE
MARKING
LVCH16374A
LVCH16374A
LDH374A
LDH374A
鈥?Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
錚?/div>
2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1

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    16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
    TI

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