鈥?/div>
Auto-bias circuit
Sync tip clamping circuit (luminance signal)
Center bias circuit (chrominance signal)
Sample-and-hold circuit
PLL 3脳 circuit
3路fsc clock output circuit
RD voltage generation step-up circuit
Features
鈥?5 V single-voltage power supply
鈥?On-chip 3脳 PLL circuit for 3路fsc operation from an fsc
(4.43 MHz) input
鈥?Supports PAL/GBI and 4.43 NTSC systems, selected by
a control pin input
鈥?Includes an on-chip comb filter for chrominance signal
crosstalk exclusion. This adjustment-free circuit
provides high-precision comb characteristics.
鈥?Peripheral circuits included on chip to allow operation
with minimal external circuits.
鈥?Positive-phase signal input, positive phase signal output
(luminance signal)
Package Dimensions
unit: mm
3111-MFP14S
[LC89975M]
Functions
鈥?CCD shift register (for chrominance and luminance
signals)
鈥?CCD drive circuit
鈥?Circuit for switching the number of CCD stages
鈥?CCD signal addition circuit
SANYO: MFP14S
Specifications
Absolute Maximum Ratings
at Ta = 25擄C
Parameter
Supply voltage
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
V
DD
Pdmax
Topr
Tstg
Conditions
Ratings
鈥?.3 to +6.0
250
鈥?0 to +60
鈥?5 to +150
Unit
V
mW
擄C
擄C
Recommended Conditions
at Ta = 25擄C
Parameter
Supply voltage
Clock input amplitude
Clock frequency
Chrominance signal input amplitude
Luminance signal input amplitude
Symbol
V
DD
V
CLK
F
CLK
V
IN-C
V
IN-Y
Sine wave
Conditions
min
4.75
300
鈥?/div>
鈥?/div>
鈥?/div>
typ
5.00
500
4.43361875
350
400
max
5.25
1000
鈥?/div>
500
572
Unit
V
mVp-p
MHz
mVp-p
mVp-p
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
41596HA (OT) No. 5391-1/7
next