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LC8900KQ Datasheet

  • LC8900KQ

  • Digital Audio Interface Receiver

  • 12頁

  • SANYO

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Ordering number : EN4128B
CMOS LSI
LC8900KQ
Digital Audio Interface Receiver
Preliminary
Overview
The LC8900KQ is a CMOS LSI circuit chip that can be
used to enable the EIAJ CP-1201 formatted data
transmission between digital audio equipment. It is used
by the receiving end and operates synchronously with
input signals. This chip demodulates input signals into
normally-formatted signals.
Applicational and Functional Concept
Features
鈥?On-chip PLL circuit: enables the LSI operation to be
synchronous to the transmitted EIAJ format input
signals.
鈥?Four input pins and one output pin: The output pin
enables the input data to be sent as they are.
鈥?Two data output function modes: 20-bit data LSB first
mode and 16-bit data MSB first mode.
鈥?Four output clocks: Bit clock, LRCK, 384Fs and 256Fs.
All these clocks are synchronized to the data.
鈥?Various signal outputs: copy inhibit, emphasis on:off
control, user鈥檚 bit, validity flag and sampling frequency.
鈥?LPF time constant select mode: This function can be
used in the PLL lock-up state.
鈥?Error detect signal output: If an input data error is
detected, this LSI circuit chip outputs the error signal.
In this case, the previous data will be output by the chip.
鈥?Lock-up signal output: This signal is output when the
internal PLL (Phase Locked Loop) block of the LSI
circuit chip is locked.
鈥?The chip has the pin to receive a signal for stopping the
PLL operation.
鈥?Control and processing mode via microcontroller
interface: input pin select, copy information and
sampling frequency output.
鈥?Each input pin has an internal amplifier circuit.
鈥?Si gate, CMOS process technology and single 5V power
supply applicational and functional concept.
Package Dimensions
unit:mm
3148-QFP44MA
[LC8900KQ]
SANYO: QIP44MA
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
83096HA (OT)/7062JN No. 4128-1/12

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