鈥?/div>
LCD Interface
YUV422 (8-bit) format. Maximum VGA size : 640脳480.
MCKI : System clock supplied to the CCD/CMOS module.
PCLK : Dot clock output from the CCD/CMOS module.
80-system 16-bit bus (D15-D0, WR, RD, A2-0, CS)
Accessible to the JPEG controller, control register including I
2
C master, JPEG code buffer,
thumbnail image buffer, OSD display buffer, and LCD command buffer.
Connects the chip to the LCD controller system bus with the 80-system 16-bit bus interface.
It is accessible by switching automatically the two masters, host CPU or LSI image-
processing unit. Output image from LSI is RGB565 (16-bit) or RGB666
(18-bit, 9-bit脳2, etc.). Maximum display size is 320脳240 (without OSD)
or 320脳200 (with OSD). Camera image display to the sub LCD is possible.
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91004 JO IM No.8075-1/11