音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

LC78626 Datasheet

  • LC78626

  • Sanyo Semicon Device [DSP for Compact Disk Players]

  • SANYO

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

Ordering number : EN5692
CMOS LSI
LC78626E
DSP for Compact Disk Players
Overview
The LC78626E is a monolithic compact disk player signal
processing and servo control CMOS IC equipped with an
internal anti-shock control function. Designed for total
functionality including support for EFM-PLL, and one-bit
D/A converter, and containing analog low-pass filter, the
LC78626E provides optimal cost-performance for low-end
CD players that provide anti-shock systems. The basic
functions provided by this IC include modulation of the
EFM signal from the optical pick-up, deinterleaving,
detection and correction of signal errors, prevention of a
maximum of approximately 10 seconds of skipping, signal
processing such as digital filtering (which is useful in
reducing the cost of the player), and processing of a
variety of servo-related commands from the
microprocessor.
鈥?After the subcode Q signal passes the CRC check, it is
output to the microprocessor through a serial
transmission (LSB first).
鈥?The demodulated EFM signal is buffered in the internal
RAM, which is able to absorb 鹵 4 frame's worth of jitter
resulting from variations in the disk rotation speed.
鈥?The demodulated EFM signal is unscrambled to a
specific sequence, and deinterleaving is performed.
鈥?Error detection and correction is performed, as is a flag
process. (C1: two error/C2: two error correction
method.)
鈥?The C2 flag is set after referencing the C1 flag and the
results of the C2 check, where the signal from the C2
flag is interpolated or held at its previous level. The
interpolation circuit uses double interpolation. When
there are two or more C2 flags in a row, the previous
value is held.
Continued on next page.
Functions
鈥?When an HF signal is input, it is sliced to precise levels
and converted to an EFM signal. The phase is compared
with the internal VCO and a PLL clock is reproduced at
an average frequency of 4.3218 MHz.
鈥?Precise timing for a variety of required internal timing
needs (including the generation of the reference clock) is
produced by the attachment of an external 16.9344 MHz
crystal oscillator.
鈥?The speed of revolution of the disk motor is controlled
by the frame phase difference signal generated by the
playback clock and the reference clock.
鈥?The frame synchronizing signal is detected, stored, and
interpolated to insure stable data read back.
鈥?The EFM signal is demodulated and converted to 8-bit
symbolic data.
鈥?The demodulated EFM signal is divided into subcodes
and output to the external microprocessor. (Three
general I/O ports are shared [exclusively] for this
purpose.)
Package Dimensions
unit: mm
3151-QFP100E (FLP100)
[LC78626E]
SANYO: QIP100E (FLP100)
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
13098HA(OT) No. 5692-1/32

LC78626相關(guān)型號PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！