鈥?/div>
鈥?Output ports: 28
鈥?I/O ports: 25 (These pins can be switched between
input and output in bit units.)
PLL block
鈥?Built-in sub-charge pump for high-speed locking
鈥?Support for dead zone control
鈥?Built-in unlock detection circuit
鈥?Twelve reference frequencies: 1, 3, 3.125, 5, 6.25, 9,
10, 12.5, 25, 30, 50 and 100 kHz
Universal counter: 20 bits
Supports frequency and period
measurement with counting periods
of 1, 4, 8 and 32 ms.
Timers: Timer interrupt periods
100 碌s, 1 ms, 2 ms, 5 ms, 10 ms, 50 ms, 125 ms
and 250 ms
Beep: Six frequencies: 2.08 kHz, 2.25 kHz, 2.5 kHz,
3.0 kHz, 3.75 kHz, 4.17 kHz.
Reset: Built-in voltage detection type reset circuit
Cycle time: 1.33 碌s (all instructions execute in one
cycle)
Halt mode: The microcontroller operating clock is
stopped in halt mode.
There are four types of event that clear halt
mode: interrupt requests, timer FF
overflows, key inputs, and hold pin inputs.
Operating supply voltage: 4.5 to 5.5 V (3.5 to 5.5 V
when only the controller
block operates)
Package: QFP80E (QIP80E)
OTP version: LC72P366
Development tools: Emulator .................RE32N
Evaluation chip.......LC72EV350
Evaluation chip board
................................EB-72EV350
This LSI can easily use CCB that is SANYO鈥檚 original bus format.
鈥?CCB is a trademark of SANYO ELECTRIC CO., LTD.
鈥?CCB is SANYO鈥檚 original bus format and all the bus
addresses are controlled by SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
63096HA (OT)/62295TH (OT) No. 5065-1/13