10 k鈩?/div>
FIGURE 1. Offset Voltage Adjustment for Inverting
Amplifiers Using 10 k鈩?Source Resistance or Less
The circuit shown in
Figure 1
is used to balance out the
offset voltage of inverting amplifiers having a source resis-
tance of 10 k鈩?or less. A small current is injected into the
summing node of the amplifier through R
1
. Since R
1
is 2000
times as large as the source resistance the voltage at the
arm of the pot is attenuated by a factor of 2000 at the
summing node. With the values given and
鹵
15V supplies the
output may be zeroed for offset voltages up to
鹵
7.5 mW.
If the value of the source resistance is much larger than 10
k鈩? the resistance needed for R
1
becomes too large. In this
case it is much easier to balance out the offset by supplying
a small voltage at the non-inverting input of the amplifier.
Figure 2
shows such a scheme. Resistors R
1
and R
2
divide
the voltage at the arm of the pot to supply a
鹵
7.5 mW
adjustment range with
鹵
15V supplies.
This adjustment method is also useful when the feedback
element is a capacitor or non-linear device.
LB-9
漏 2002 National Semiconductor Corporation
AN008460
www.national.com
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