Freescale Semiconductor, Inc.
Fact Sheet
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by LATEWRITEFACT/D
L
ATE
W
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A
RCHITECTURE
F
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SRAM
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FOR
H
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RISC
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ELECOMMUNICATIONS
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Late Write FSRAMs are primarily designed to provide RISC CPUs with high performance L2 cache. By offering
a variety of speed grades and I/Os; Motorola Late Write SRAMs can be used as L2 cache by MIPS, PA RISC,
Alpha, UltraSPARC, and Power RISC CPUs. Late Writes also provide a high bandwidth cache solution for
embedded processors and ASICs in switching applications.
The major advantage of the Late Write architecture is that write data is supplied to the memory one clock cycle
after address. Back to back read to write access is possible with the register/latch devices.
These parts are JEDEC standard pinout and are pin for pin compatible with our competitors Late Write devices.
Freescale Semiconductor, Inc...
Product Description
The 4 megabit and 8 megabit Late Write FSRAMs are high speed synchronous SRAMs designed to provide high
performance in secondary cache and ATM switch, Telecom, and other high speed memory applications. The
current 4 megabit devices are organized as 256K words by 18 bits and 128K words by 36 bits and are
fabricated in Motorola's state of the art MOS 11 facility. The 8 megabit devices, and a new 4 megabit device,
are fabricated in Motorola's MOS 13 facility using a high performance CMOS process, with copper
interconnect. The 8 megabit devices are organized as 512K words by 18 bits and 256K words by 36 bits.
For single clock devices, the differential CK clock inputs control the timing of read/write operations of the
RAM. At the rising edge of the CK clock all addresses, write enables, and synchronous selects are registered.
An internal buffer and special logic enable the memory to accept write data on the rising edge of the CK
clock, a cycle after address and control signals. For register/register devices, read data is available after the
next rising CK clock edge. For register/latch devices, read data is available at the falling edge of the CK clock.
The synchronous write and byte enables, allow writing to individual bytes or the entire word.
Features
HSTL, Register/Register (Pipelined)
Single Clock Features
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Byte Write Control
1.8 V, 2.5 V, 3.3 V Operation
Boundary Scan (JTAG) IEEE 1149.1
Compatible
Differential Clock Inputs
Optional x18 or x36 Organization
119 Bump, 50 mil (1.27 mm) Pitch,
14 mm x 22 mm Plastic Ball Grid Array
(PBGA) and Flip Chip PBGA Packages
Available
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Extended HSTL
I/O (JEDEC Standard
JESD8 6 Class I Compatible)
HSTL
User Selectable Input Trip Point
Programmable Impedance Output Drivers
Register/Register Synchronous Operation
3/3.3/3.7/4/4.4/5/6/7/8 ns Cycle
(4 megabit)
3.0/3.3/3.7/4.0/4.4/5.0 ns Cycle
(8 megabit)
Continued on back
For More Information On This Product,
Go to: www.freescale.com
REV 3
3/18/99
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LATEWRITE Fact Sheet
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