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L6000 Datasheet

  • L6000

  • SINGLE CHIP READ & WRITE CHANNEL

  • 279.74KB

  • 24頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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L6000
SINGLE CHIP READ & WRITE CHANNEL
ADVANCE DATA
SUPPORTS 9-32Mbit/s DATA RATE OPERA-
TION IN RLL [1,7] CONSTRAINT
- Data Rate is Programmable
SUPPORTS ZONED BIT RECORDING AP-
PLICATIONS
LOW POWER OPERATION (500mW TYPI-
CAL @ 5V @ 32Mbits/Sec
PROVIDES PROGRAMMABILITY THROUGH
SERIAL MICROPROCESSOR INTERFACE
AND INTERNAL REGISTERS
- Bi-directional access to internal registers of
pulse detector, filter, servo demodulator,
frequency synthesizer and data separator.
PROGRAMMABLE POWER DOWN MODES
Full power-down mode (5mW max.)
POWER SUPPLY RANGE 4.3 to 5.5V
DESCRIPTION
The L6000 is a 5V single chip read channel IC. It
contains all the functions needed to implement a
high performance read channel including the
PIN CONNECTION
(Top view)
TQFP64
(10 x 10)
ORDERING NUMBER:
L6000
OPERATING TEMPERATURE:
0擄C to 70擄C
pulse detector, programmable active filter, servo
demodulator, frequency sinthesizer, and data
separator, at data rates up to 32 Mbit/s. A single
external resistor sets the reference current for the
internal DAC which, in turn, fixes the data rate.
This device is programmed through a serial port
and banks of internal registers. It is fully compat-
ible with zoned bit recording applications. Exter-
nal components do not need to be changed when
switching between zones. The L6000 is manufac-
tured using an advanced BiCMOS technology.
HOLD SRV AGC
RESET CAP A/B
SERVO TC RES
GND CORE DIG
GND DATA SEP
34
POSITION OUT
SERVO REF V
DATA TC RES
LATCH CAP A
LATCH CAP B
SERVO GATE
HOLD CAP A
HOLD CAP B
DAC TP OUT
SERVO BYP
48
LEVEL
LEVEL REF V
CLOC K PATH
CLOC K PATH
DATA PATH
DATA PATH
FI LT NORM OUT
FI LT NORM OUT
FI LT DIFF OUT
FI LT DIFF OUT
VCC PULSE DET
FILT ER IN
FILT ER IN
PTAT R
AGC O UT
AGC O UT
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DATA SEP FLT
DATA SEP FLT
VCC DATA SEP
READ DATA I/O
ADDR MARK DET
READ REF CLOC K
WRIT E CLOC K
MULT T P1
MULT T P2
GND I/O
WRIT E DATA NR2 IN
READ NR2 O UTPUT
WRIT E DATA
VCC I/O
WRIT E GATE
READ GATE
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SERIAL CLOCK +
GND PULSE DET
HOLD DATA AGC
REFERENCE FIN
GND FREO SYN
FREQ OUT TP
SERIAL DATA I/O
VCC FREQ SYN
VCC CORE DIG
FREQ SYN FLT
SERIAL ENABLE
FREQ SYN FLT
PWRDN MODE
DATA BYP
AGC IN
AGC IN
DS IREF
M92L6000-01
August 1993
1/24
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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