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L4985 Datasheet

  • L4985

  • 23頁

  • ETC

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L4985
HIGH EFFICIENCY SWITCHING REGULATOR
PRODUCT PREVIEW
OPERATING INPUT VOLTAGE:
FROM 4.5V TO 21V
HIGHEFFICIENCY 3A STEP DOWN CONVERTER
3A @ 3.3V OUTPUT VOLTAGE FROM 4.5V
INPUT VOLTAGE
ADJUSTABLE OUTPUT VOLTAGE
FROM 1.28V
GATE DRIVER FOR SYNCHRONOUS
RECTIFICATION
100% MAXIMUM DUTY CYCLE
INTERNAL CURRENT LIMIT
SOFT START, RESET SIGNAL,
THERMAL SHUTDOWN
AUXILIARY CONVERTER WITH 40V
OPEN DRAIN SWITCH DELIVERING 5W
@ V
IN
= 12V
1.7A PEAK CURRENT INTERNALLY
LIMITED (TYP)
POWER MANAGEMENT
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MULTIPOWER BCD TECHNOLOGY
POWERDIP 16+2+2
SO20
ORDERING NUMBERS:
L4985 (Powerdip)
L4985D (SO20)
DESCRIPTION
This high efficiency DC-DC converter is a mono-
lithic device developed to generate all the volt-
ages required in multioutputs DC-DC converters,
in particular when the supply voltage is a battery,
and isolation is not needed.
Designed to start to operate at an input voltage as
low as 4.5V up to 21V, the device takes the ad-
vantages offered by our proprietary BCD Mul-
tipower technology to deliver 3A to the load on
the stepdown section, and to manage 1.5A peak
current on the open drain section.
The packages proposed are in plastic dual in line,
Powerdip 20 (16+2+2) for standard assembly,
and SO20L for SMD assembly.
This device is constitueed by two major sections:
one section is a stepdown regulator, and the
other one is a flexible regulator with open drain
output DMOS transistor, source grounded, for fly-
back/forward topologies for multioutputs, or step-
up topology when a single voltage higher than the
supply one is requested.
Step Down Converter Section
The stepdown section, delivering to the load up to
3A current, at an output voltage adjustable from
1.28V up to 16V, works in voltage mode, fixed fre-
quency, with no limitation on the max duty cycle.
This section has been designed to maximise the
efficiency minimising the conduction losses and
the quiescent current.
An internal step-up converter using a small chip
inductor and a filter capacitor provides voltage
and energy the gate driver of the internal N-chan-
nel DMOS transistor of 0.1鈩?typ of R
dson
, and the
driver of an external DMOS transistor that should
require no more than 30nC of gate charge, at
100KHz.
The gate driver pin can be left open if the use of a
Schottky diode is preferred.
An internal pulse by pulse current limiting protects
the device it self and the load from overload and
short circuit conditions.
A reset block, monitoring the feedback voltage,
with an programmable reset delay time, gener-
ates a reset signal for the microprocessor.
The reset output is an open drain.
Moreover, the DIS1 pin, active low, will inhibit the
whole device, reducing to leakage only the cur-
rent consumption from the battery.
March 1995
1/23
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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