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L-FW802B-DB Datasheet

  • L-FW802B-DB

  • Low-Power PHY IEEE㈢ 1394A-2000 Two-Cable Transceiver/Arbite...

  • 26頁

  • AGERE

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Data Sheet, Rev. 3
May 2004
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FW802B Low-Power PHY
IEEE
廬
1394A-2000
Two-Cable Transceiver/Arbiter Device
Distinguishing Features
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Fully supports suspend/resume.
Supports PHY-link interface initialization and reset.
Supports
1394a-2000
register set.
Supports LPS/link-on as a part of PHY-link inter-
face.
Supports provisions of
IEEE 1394-1995 Standard
for a High Performance Serial Bus.
Fully interoperable with
FireWire
廬
implementation
of
IEEE 1394-1995.
Reports cable power fail interrupt when voltage at
CPS pin falls below 7.5 V.
Provides separate cable bias and driver termination
voltage supply for each port.
Compliant with
IEEE
Standard
1394a-2000,
IEEE
Standard for a High Performance Serial Bus
Amendment 1.
Low-power consumption during powerdown or
microlow-power sleep mode.
Supports extended BIAS_HANDSHAKE time for
enhanced interoperability with camcorders.
While unpowered and connected to the bus, the
device will not drive TPBIAS on a connected port
even if receiving incoming bias voltage on that port.
Does not require external filter capacitors for PLL.
Does not require a separate 5 V supply for 5 V link
controller interoperability.
Interoperable across
1394
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cable with
1394
physi-
cal layers (PHY) using 5 V supplies.
Interoperable with
1394
link-layer controllers using
5 V supplies.
1394a-2000
compliant common-mode noise filter
on incoming TPBIAS.
Powerdown features to conserve energy in battery-
powered applications include:
鈥?Device powerdown pin.
鈥?Link interface disable using LPS.
鈥?Inactive ports power down.
鈥?Automatic microlow-power sleep mode during
suspend.
Interface to link-layer controller supports Annex J
electrical isolation as well as bus-keeper isolation.
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Other Features
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64-pin TQFP package. (Lead-free package also
available. See ordering information on page 25.)
Single 3.3 V supply operation.
Data interface to link-layer controller provided
through 2/4/8 parallel lines at 50 Mbits/s.
25 MHz crystal oscillator and PLL provide a
50 MHz link-layer controller clock as well as trans-
mit/receive data at 100 Mbits/s, 200 Mbits/s, and
400 Mbits/s.
Node power-class information signaling for system
power management.
Multiple separate package signals provided for ana-
log and digital supplies and grounds.
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Features
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Description
The Agere Systems Inc. FW802B device provides
the analog physical layer functions needed to imple-
ment a two-port node in a cable-based
IEEE 1394-
1995 and
IEEE 1394a-2000
network.
Each cable port incorporates two differential line
transceivers. The transceivers include circuitry to
monitor the line conditions as needed for determin-
ing connection status, for initialization and arbitration,
and for packet reception and transmission. The PHY
is designed to interface with a link-layer controller
(LLC).
Provides two fully compliant cable ports at
100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.
Fully supports
1394
Open HCI requirements.
Supports arbitrated short bus reset to improve
utilization of the bus.
Supports ack-accelerated arbitration and fly-by con-
catenation.
Supports connection debounce.
Supports multispeed packet concatenation.
Supports PHY pinging and remote PHY access
packets.
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