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L-FW32206T100 Datasheet

  • L-FW32206T100

  • 1394a PCI PHY/Link Open Host Controller

  • 86頁

  • AGERE

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Data Sheet, Rev. 1
December 2005
鈩?/div>
FW322 06 T100
1394a PCI PHY/Link Open Host Controller
Features
1394a-2000 OHCI link and PHY core function in a sin-
gle device:
鈥?/div>
100-pin TQFP package (also available in a lead-free
package; see ordering information on page 85.)
鈥?Single-chip link and PHY enable smaller, simpler,
more efficient motherboard and add-in card designs
鈥?Enables lower system costs
鈥?Leverages proven 1394a-2000 PHY core design
鈥?Demonstrated compatibility with current
Microsoft
Windows
廬
drivers and common applications
鈥?/div>
Demonstrated interoperability with existing, as well
as older, 1394 consumer electronics and peripherals
products
鈥?Feature-rich implementation for high performance in
common applications
鈥?Supports low-power system designs (CMOS imple-
mentation, power management features)
OHCI:
鈥?Complies with the
1394 OHCI 1.1 Specification
鈥?OHCI 1.0 backwards compatible鈥攃onfigurable via
EEPROM to operate in either OHCI 1.0 or OHCI 1.1
mode
鈥?Complies with
Microsoft Windows
logo program
system and device requirements
鈥?Listed on
Windows
hardware compatibility list
http://www.microsoft.com/hcl/results.asp
鈥?Compatible with
Microsoft Windows
and
MacOS
廬
operating systems
鈥?4 Kbyte isochronous transmit FIFO
鈥?2 Kbyte asynchronous transmit FIFO
鈥?4 Kbyte isochronous receive FIFO
鈥?2 Kbyte asynchronous receive FIFO
鈥?Dedicated asynchronous and isochronous
descriptor-based DMA engines
鈥?Eight isochronous transmit contexts
鈥?Eight isochronous receive contexts
鈥?Prefetches isochronous transmit data
鈥?Supports posted write transactions
鈥?Supports parallel processing of incoming physical
read and write requests
鈥?Supports notification (via interrupt) of a failed
register access
鈥?Information normally in the EEPROM can be pro-
grammed into the system BIOS.
1394a-2000 PHY core:
鈥?Compliant with
IEEE
廬
1394a-2000,
Standard for a
High Performance Serial Bus
(Supplement)
鈥?Provides two fully compliant cable ports, each
supporting 400 Mbits/s, 200 Mbits/s, and
100 Mbits/s traffic
鈥?Supports extended BIAS_HANDSHAKE time for
enhanced interoperability with camcorders
鈥?While unpowered and connected to the bus, will not
drive TPBIAS on a connected port even if receiving
incoming bias voltage on that port
鈥?Does not require external filter capacitor for PLL
鈥?Supports link-on as a part of the internal
PHY core-link interface
鈥?25 MHz crystal oscillator and internal PLL provide a
50 MHz
internal
link-layer controller clock as well
as
transmit/receive data at 100 Mbits/s, 200 Mbits/s,
and 400 Mbits/s.
鈥?Interoperable across 1394 cable with 1394 physical
layers (PHY core) using 5 V supplies
鈥?Provides node power-class information signaling for
system power management
鈥?Supports ack-accelerated arbitration and fly-by
concatenation
鈥?Supports arbitrated short bus reset to improve
utilization of the bus
鈥?Fully supports suspend/resume
鈥?Supports connection debounce
鈥?Supports multispeed packet concatenation
鈥?Supports PHY pinging and remote PHY access
packets
鈥?Reports cable power fail interrupt when voltage at
CPS pin falls below 7.5 V
Link:
鈥?Cycle master and isochronous resource manager
capable
鈥?Supports 1394a-2000 acceleration features
PCI:
鈥?Revision 2.2 compliant
鈥?33 MHz/32-bit operation
鈥?Programmable burst size thresholds for PCI data
transfer
鈥?Supports optimized memory read line, memory read
multiple, and memory write invalidate burst
commands
鈥?Supports
PCI Bus Power Management Interface
Specification
v.1.1.
Note:
This device does not support D3cold wakeup,
CLKRUN protocol,
mini PCI
廬
applications, and
CardBus applications. Use the FW322 06 120-pin
TQFP device if one or more of these features are
needed.

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