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L-FW322-06-DB Datasheet

  • L-FW322-06-DB

  • PCI PHY/Link Open Host Controller Interface

  • 965.42KB

  • 92頁

  • AGERE

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Data Sheet, Rev. 1
December 2005
鈩?/div>
FW322 06 1394a
PCI PHY/Link Open Host Controller Interface
Features
1394a-2000 OHCI link and PHY core function in a
single device:
鈥?Single-chip link and PHY enable smaller, simpler,
more efficient motherboard and add-in card
designs
鈥?Enables lower system costs
鈥?Leverages proven 1394a-2000 PHY core design
鈥?Demonstrated compatibility with current
Microsoft
廬
Windows
廬
drivers and common appli-
cations
鈥?Demonstrated interoperability with existing, as
well as older, 1394 consumer electronics and
peripherals products
鈥?Feature-rich implementation for high perfor-
mance in common applications
鈥?Supports low-power system designs (CMOS
implementation, power management features)
鈥?Provides LPS, LKON, and CNA outputs to sup-
port legacy power management implementations
OHCI:
鈥?Complies with the 1394
OHCI 1.1 Specification
鈥?OHCI 1.0 backwards compatible鈥攃onfigurable
via EEPROM to operate in either OHCI 1.0 or
OHCI 1.1 mode
鈥?Complies with
Microsoft Windows
logo program
system and device requirements
鈥?Listed on
Windows
hardware compatibility list
http://www.microsoft.com/windows/catalog/
鈥?Compatible with
Microsoft Windows
and
MacOS
廬
operating systems
鈥?4 Kbyte isochronous transmit FIFO
鈥?2 Kbyte asynchronous transmit FIFO
鈥?4 Kbyte isochronous receive FIFO
鈥?2 Kbyte asynchronous receive FIFO
鈥?Dedicated asynchronous and isochronous
descriptor-based DMA engines
鈥?Eight isochronous transmit contexts
鈥?Eight isochronous receive contexts
鈥?Prefetches isochronous transmit data
鈥?Supports posted write transactions
鈥?Supports parallel processing of incoming phys-
ical read and write requests
鈥?Supports notification (via interrupt) of a failed
register access
鈥?May be used without an EEPROM when the sys-
tem BIOS is programmed with the EEPROM con-
tents.
1394a-2000 PHY core:
鈥?Compliant with
IEEE
廬
1394a-2000,
Standard for
a High Performance Serial Bus
(Supplement)
鈥?Provides two fully compliant cable ports, each
supporting 400 Mbits/s, 200 Mbits/s, and
100 Mbits/s traffic
鈥?Supports extended BIAS_HANDSHAKE time for
enhanced interoperability with camcorders
鈥?While unpowered and connected to the bus, will
not drive TPBIAS on a connected port even if
receiving incoming bias voltage on that port
鈥?Does not require external filter capacitor for PLL
鈥?Supports link-on as a part of the internal
PHY core-link interface
鈥?25 MHz crystal oscillator and internal PLL
provide a 50 MHz internal link-layer controller
clock as well as transmit/receive data at
100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.
鈥?Interoperable across 1394 cable with 1394 phys-
ical layers (PHY core) using 5 V supplies
鈥?Provides node power-class information signaling
for system power management
鈥?Supports ack-accelerated arbitration and fly-by
concatenation
鈥?Supports arbitrated short bus reset to improve
utilization of the bus
鈥?Fully supports suspend/resume
鈥?Supports connection debounce
鈥?Supports multispeed packet concatenation
鈥?Supports PHY pinging and remote PHY access
packets
鈥?Reports cable power fail interrupt when voltage
at CPS pin falls below 7.5 V
鈥?Provides separate cable bias and driver termina-
tion voltage supply for each port
Link:
鈥?Cycle master and isochronous resource
manager capable
鈥?Supports 1394a-2000 acceleration features

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