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Integrated switch with five MACs and five Fast Ethernet
transceivers fully compliant to IEEE 802.3u standard
Shared memory based switch fabric with fully non-
blocking configuration
10BaseT, 100BaseTX and 100BaseFX modes (FX
in Ports 4 & 5)
Dual MII configuration: MII-Switch (MAC or PHY
mode MII) and MII-P5 (PHY mode MII)
VLAN ID tag/untag options, per-port basis
Programmable rate limiting, ingress and egress port, rate
options for high and low priority, per port basis
Flow control or drop packet rate limiting (ingress port)
Broadcast storm protection with % control鈥揼lobal and
per-port basis
Optimization for fiber-to-copper media conversion
Full-chip hardware power-down support (register
configuration not saved)
Per-port based software power-save on PHY (idle link
detection, register configuration preserved)
Block Diagram
Auto
MDI/MDIX
Auto
MDI/MDIX
Auto
MDI/MDIX
Auto
MDI/MDIX
Auto
MDI/MDIX
MII-P5
MDC, MDI/O
MII-SW or SNI
LED0[5:1]
LED1[5:1]
LED2[5:1]
10/100
T/Tx 1
10/100
T/Tx 2
10/100
T/Tx 3
10/100
T/Tx/Fx 4
10/100
T/Tx/Fx 5
10/100
MAC 1
1K look-up
Engine
FIFO, Flow Control, VLAN Tagging ,Priority
10/100
MAC 2
10/100
MAC 3
10/100
MAC 4
10/100
MAC 5
SNI
Queue
Mgmnt
Buffer
Mgmnt
Frame
Buffers
LED I/F
Control
Registers
EEPROM
I/F
Micrel Semiconductor
TEL:
1.800.401.9572
FAX:
1.408.474.0159
HTTP://
www.micrel.com
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