KS51840
DESCRIPTION
KS51840, a 4-bit single-chip CMOS microcontroller, consists of the reliable SMCS-51 CPU core with on-chip
ROM and RAM. Eight input pins and 11 output pins provide the flexibility for various I/O requirements. Auto
reset circuit generates reset pulse every certain period, and every halt mode termination time. The KS51840
microcontroller has been designed for use in small system control applications that require a low-power,
cost-sensitive design solution. In addition, the KS51840 has been optimized for remote control transmitter.
FEATURES
ROM Size
1,024 bytes
RAM Size
32 nibbles
Instruction Set
39 instructions
Instruction Cycle Time
13.2 碌sec at Fxx=455 kHz
Input Ports
Two 4-bit ports(24 pins)/One 4-bit port, one 2-bit ports(20 pins)
Output Ports
One 4-bitport,Seven1-bitports(24pins)/One 4-bit port, Five1-bit ports(20pins)
Built-in Oscillator
Crystal/Ceramic resonator
Built-in Power-on reset and auto reset circuit for generating reset pulse every 131072/Fxx(288ms at Fxx=455kHz)
Four Transmission Frequencies
Fxx/12 (1/4 duty), Fxx/12 (1/3 duty), Fxx/8 (1/2 duty), and
no-carrier frequency
Supply Voltage
1.8V鈥?.6V(Fosc:250kHz鈥?.9MHz),2.2V鈥?.6V(Fosc:4MHz鈥?MHz)
Power Consumption
Halt mode: 1 碌A(chǔ) (maximum)
Normal mode: 0.5 mA (typical)
Operating temperature
-20擄C to 85擄C
Package Type
24 SOP, 20 DIP, 20 SOP
Oscillator Frequency divide select Mask Option= Fosc or Fosc/8
BLOCK DIAGRAM
P2.1 - P2.6
6
P2-output Latch
5
8
Internal P2.13
ROM
64x16x8 bits
4
PA
6
PC
RAM
16x2x4bits
2
4
H
16
L Decoder
1
4
4
L
4
4
PB
3-Level Stack
4
MUX
ALU & A
4
P3 Output Register
( PR )
SF
4
Internal
P2.0
4
4
4
P1.0 - P1.3
P0.0 - P0.3
P3.0 - P3.3
Internal P2.9 and P2.10
Fxx/8 (1/2)
Fxx/12 (1/3)
Fxx/12 (1/4)
DIV
OSC
Auto Reset
HALT
Internal P2.12
No carrier
P2.0/REM
XI XO
S MSUN G
MSU N
ELECTRONICS
1鈥?
1
2
3
