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KM48C2000B, KM48C2100B

KM48V2000B, KM48V2100B

2M x 8Bit CMOS Dynamic RAM with Fast Page Mode

DESCRIPTION

CMOS DRAM

This is a family of 2,097,152 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells

within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K Ref.), access time (-5,-6 or -7), power con-

sumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-

before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version.

This 2Mx8 Fast Page Mode DRAM family is fabricated using Samsung's advanced CMOS process to realize high band-width, low power

consumption and high reliability.

It may be used as graphic memory unit for microcomputer, personal computer and portable machines.

FEATURES

隆脺

隆脺

Fast Page Mode operation

Byte/Word Read/Write operation

CAS-before-RAS refresh capability

RAS-only and Hidden refresh capability

Self-refresh capability (L-ver only)

Fast parallel test mode capability

TTL(5V)/LVTTL(3.3V) compatible inputs and outputs

Early Write or output enable controlled write

JEDEC Standard pinout

Available in Plastic SOJ and TSOP(II) packages

Single +5V

隆戮

10% power supply (5V product)

Single +3.3V

隆戮

0.3V power supply (3.3V product)

Part Identification

- KM48C2000B/B-L (5V, 4K Ref.)

- KM48C2100B/B-L (5V, 2K Ref.)

- KM48V2000B/B-L (3.3V, 4K Ref.)

- KM48V2100B/B-L (3.3V, 2K Ref.)

隆脺

隆脺

隆脺

隆脺

隆脺

隆脺

隆脺

Active Power Dissipation

Unit : mW

Speed

4K

-5

-6

-7

324

288

252

3.3V

2K

396

360

324

4K

495

440

385

5V

隆脺

隆脺

隆脺

2K

隆脺

605

隆脺

550

495

FUNCTIONAL BLOCK DIAGRAM

隆脺

Refresh Cycles

Part

NO.

C2000B

V2000B

C2100B

V2100B

V

CC

5V

3.3V

5V

3.3V

2K

32ms

Refresh

cycle

4K

Refresh period

Normal

64ms

128ms

Refresh Timer

Refresh Control

Refresh Counter

Memory Array

2,097,152 x 8

Cells

Row Decoder

Sense Amps & I/O

RAS

CAS

W

Control

Clocks

VBB Generator

Vcc

Vss

L-ver

Data in

Buffer

DQ0

to

DQ7

隆脺

Performance Range

Speed

-5

-6

-7

t

RAC

50ns

60ns

70ns

t

CAC

13ns

15ns

20ns

t

RC

90ns

110ns

130ns

t

PC

35ns

40ns

45ns

Remark

5V/3.3V

5V/3.3V

5V/3.3V

A0-A11

(A0 - A10)

*1

A0 - A8

(A0 - A9)

*1

Row Address Buffer

Col. Address Buffer

Column Decoder

Data out

Buffer

OE

Note)

*1

: 2K Refresh

SAMSUNG ELECTRONICS CO., LTD.

reserves the right to

change products and specifications without notice.

next

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