KM44S32030 Datasheet

IC型號：
KM44S32030
PDF描述：
8M x 4Bit x 4 Banks Synchronous DRAM
文件大小：
120.54KB
PDF頁數(shù)：
10頁
芯片廠家：
SAMSUNG

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KM44S32030

8M x 4Bit x 4 Banks Synchronous DRAM

FEATURES

鈥?JEDEC standard 3.3V power supply

鈥?LVTTL compatible with multiplexed address

鈥?Four banks operation

鈥?MRS cycle with address key programs

-. CAS Latency (2 & 3)

-. Burst Length (1, 2, 4, 8)

-. Burst Type (Sequential & Interleave)

鈥?All inputs are sampled at the positive going edge of the system

clock.

鈥?Burst Read Single-bit Write operation

鈥?DQM for masking

鈥?Auto & self refresh

鈥?64ms refresh period (4K cycle)

Preliminary

CMOS SDRAM

GENERAL DESCRIPTION

The KM44S32030 is 134,217,728 bits synchronous high data

rate Dynamic RAM organized as 4 x 8,388,608 words by 4 bits,

fabricated with SAMSUNG鈥瞫 high performance CMOS technol-

ogy. Synchronous design allows precise cycle control with the

use of system clock I/O transactions are possible on every clcok

cycle. Range of operating frequencies, programmable burst

length and programmable latencies allow the same device to be

useful for a variety of high bandwidth, high performance mem-

ory system applications.

ORDERING INFORMATION

Part NO.

KM44S32030T-G/F8

KM44S32030T-G/FH

KM44S32030T-G/FL

KM44S32030T-G/F10

MAX Freq.

125MHz

100MHz

LVTTL

54pin

TSOP(II)

Interface Package

FUNCTIONAL BLOCK DIAGRAM

I/O Control

LWE

Data Input Register

LDQM

Bank Select

8M x 4

Sense AMP

8M x 4

Refresh Counter

Output Buffer

Row Decoder

Row Buffer

DQi

Address Register

CLK

ADD

Column Decoder

Col. Buffer

Latency & Burst Length

LRAS

LCBR

LCKE

LRAS

LCBR

LWE

LCAS

Programming Register

LWCBR

LDQM

Timing Register

CLK

CKE

RAS

CAS

DQM

* Samsung Electronics reserves the right to

change products or specification without

notice.

REV. 2 Mar. '98

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