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KM44C4103C Datasheet

  • KM44C4103C

  • 4M x 4Bit CMOS Quad CAS DRAM with Fast Page Mode

  • 20頁

  • SAMSUNG   SAMSUNG

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KM44C4003C, KM44C4103C
CMOS DRAM
4M x 4Bit CMOS Quad CAS DRAM with Fast Page Mode
DESCRIPTION
This is a family of 4,194,304 x 4 bit Quad CAS with Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access
of memory cells within the same row. Refresh cycle (2K Ref. or 4K Ref.), access time (-5 or -6), power consumption(Normal or Low
power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only
refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. Four separate CAS pins provide for
seperate I/O operation allowing this device to operate in parity mode.
This 4Mx4 Fast Page Mode Quad CAS DRAM family is fabricated using Samsung鈥瞫 advanced CMOS process to realize high band-
width, low power consumption and high reliability.
FEATURES
鈥?/div>
Part Identification
- KM44C4003C/C-L (5V, 4K Ref.)
- KM44C4103C/C-L (5V, 2K Ref.)
鈥?Fast Page Mode operation
鈥?Four seperate CAS pins provide for separate I/O operation
鈥?CAS-before-RAS refresh capability
鈥?RAS-only and Hidden refresh capability
鈥?Self-refresh capability (L-ver only)
鈥?Fast paralleltest mode capability
鈥?TTL compatible inputs and outputs
Unit : mW
鈥?Early Write or output enable controlled write
鈥?JEDEC Standard pinout
2K
605
550
鈥?Available in Plastic SOJ and TSOP(II) packages
鈥?Single +5V鹵10% power supply
鈥?/div>
Active Power Dissipation
Refresh Cycle
4K
-5
-6
495
440
Speed
FUNCTIONAL BLOCK DIAGRAM
鈥?/div>
Refresh Cycles
Part
NO.
C4003C
C4103C
Refresh
cycle
4K
2K
Refresh period
Normal
64ms
32ms
Refresh Timer
Refresh Control
Row Decoder
Sense Amps & I/O
RAS
CAS0 - 3
W
Control
Clocks
Vcc
Vss
L-ver
128ms
VBB Generator
Data in
Buffer
鈥?/div>
Performance Range
Speed
-5
-6
Refresh Counter
t
RAC
50ns
60ns
t
CAC
13ns
15ns
t
RC
90ns
110ns
t
PC
35ns
40ns
Remark
5V/3.3V
5V/3.3V
Memory Array
4,194,304 x 4
Cells
DQ0
to
DQ3
A0-A11
(A0 - A10)
*1
A0 - A9
(A0 - A10)
*1
Row Address Buffer
Col. Address Buffer
Column Decoder
Data out
Buffer
OE
Note)
*1
: 2K Refresh
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.

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