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KM44C1000D Datasheet

  • KM44C1000D

  • 1M x 4Bit CMOS Dynamic RAM with Fast Page Mode

  • 21頁(yè)

  • SAMSUNG   SAMSUNG

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KM44C1000D, KM44V1000D
CMOS DRAM
1M x 4Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 1,048,576 x 4bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells
within the same row. Power supply voltage (+5V or +3.3V), access time (-5, -6 or -7), power consumption(Normal or Low power), and
package type (SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and
Hidden refresh capabilities. Furthermore, self-refresh operation is available in 3.3V Low power version.
This 1Mx4 Fast Page Mode DRAM family is fabricated using Samsung鈥瞫 advanced CMOS process to realize high band-width, low power
consumption and high reliability. It may be used as main memory for main frames and mini computers, personal computer and high per-
formance microprocessor systems.
FEATURES
鈥?Part Identification
- KM44C1000D/D-L(5V, 1K Ref.)
- KM44V1000D/D-L(3.3V, 1K Ref.)
鈥?Fast Page Mode operation
鈥?CAS-before-RAS refresh capability
鈥?RAS-only and Hidden refresh capability
鈥?Self-refresh capability (3.3V, L-ver only)
鈥?Fast parallel test mode capability
鈥?TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
鈥?Early write or output enable controlled write
鈥?/div>
Active Power Dissipation
Unit : mW
Speed
-5
-6
-7
3.3V
-
220
200
5V
470
415
360
鈥?JEDEC Standard pinout
鈥?Available in 26(20)-pin SOJ 300mil and TSOP(II)
300mil packages
鈥?Single +5V鹵10% power supply(5V product)
鈥?Single +3.3V鹵0.3V power supply(3.3V product)
FUNCTIONAL BLOCK DIAGRAM
鈥?/div>
Refresh Cycles
Part
NO.
KM44C1000D
KM44V1000D
Refresh
cycle
1K
Refresh Period
Normal
16ms
L-ver
128ms
Refresh Timer
Refresh Control
Row Decoder
Sense Amps & I/O
Data in
Buffer
RAS
CAS
W
Control
Clocks
VBB Generator
Vcc
Vss
鈥?/div>
Performance Range
Speed
-5
-6
-7
Refresh Counter
t
RAC
50ns
60ns
70ns
t
CAC
15ns
15ns
20ns
t
RC
90ns
110n
130n
t
PC
35ns
40ns
45ns
Remark
5V only
5V/3.3V
5V/3.3V
A0~A9
Col. Address Buffer
Row Address Buffer
Memory Array
1,048,576 x4
Cells
DQ0
to
DQ3
Data out
Buffer
Column Decoder
OE
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.

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