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KM416C256D, KM416V256D

256K x 16Bit CMOS Dynamic RAM with Fast Page Mode

DESCRIPTION

CMOS DRAM

This is a family of 262,144 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells

within the same row. Power supply voltage (+5.0V or +3.3V), access time (-5,-6,-7), power consumption(Normal or Low power) and

package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and

Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 256Kx16 fast page mode DRAM family is

fabricated using Samsung's advanced CMOS process to realize high band-width, low power consumption and high reliability.

It may be used as graphic memory unit for microcomputer, personal computer and portable machines.

隆脺

Fast Page Mode operation

2 CAS Byte/Wrod Read/Write operation

CAS-before-RAS refresh capability

RAS-only and Hidden refresh capability

Self-refresh capability (L-ver only)

TTL(5V)/LVTTL(3.3V) compatible inputs and outputs

Early Write or output enable controlled write

JEDEC Standard pinout

Available in 40-pin SOJ 400mil and44(40)-pin

TSOP(II) 400mil packages

Triple +5V

隆戮

10% power supply(5V product)

Triple +3.3V

隆戮

0.3V power supply(3.3V product)

FEATURES

隆脺

隆脺

Part Identification

- KM416C256D/DL (5V, 512K Ref.)

- KM416V256D/DL (3.3V, 512K Ref.)

隆脺

隆脺

隆脺

隆脺

隆脺

Active Power Dissipation

Unit : mW

Speed

-5

-6

-7

3.3V(512 Ref.)

-

325

290

5V(512 Ref.)

605

495

440

隆脺

隆脺

隆脺

隆脺

隆脺

隆脺

Refresh Cycles

Part

NO.

C256D

V256D

V

CC

5V

3.3V

Refresh

cycle

512K

Refresh period

Normal

8ms

L-ver

128ms

RAS

UCAS

LCAS

W

FUNCTIONAL BLOCK DIAGRAM

Control

Clocks

Vcc

Vss

Lower

Data in

Buffer

Sense Amps & I/O

Lower

Data out

Buffer

Upper

Data in

Buffer

Upper

Data out

Buffer

VBB Generator

Refresh Timer

隆脺

Row Decoder

Performance Range:

Speed

-5

-6

-7

DQ0

to

DQ7

t

RAC

50ns

60ns

70ns

t

CAC

15ns

15ns

20ns

t

RC

90ns

10ns

130ns

t

PC

35ns

40ns

45ns

Remark

5V only

5V/3.3V

5V/3.3V

A0

.

.

A8

Refresh Control

Refresh Counter

Row Address Buffer

Col. Address Buffer

Column Decoder

Memory Array

262,144 x16

Cells

OE

DQ8

to

DQ15

SAMSUNG ELECTRONICS CO., LTD.

reserves the right to

change products and specifications without notice.

next

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