KM416C1204C Datasheet

IC型號：
KM416C1204C
PDF描述：
1M x 16Bit CMOS Dynamic RAM with Extended Data Out
文件大?。?/label>
804.20KB
PDF頁數(shù)：
35頁
芯片廠家：
SAMSUNG

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KM416C1004C, KM416C1204C

KM416V1004C, KM416V1204C

CMOS DRAM

1M x 16Bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

This is a family of 1,048,576 x 16 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of

memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K

Ref.), access time (-45, -5 or -6), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of

this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh

operation is available in L-version. This 1Mx16 EDO Mode DRAM family is fabricated using Samsung鈥?s advanced CMOS process to

realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal

computer and portable machines.

FEATURES

鈥?/div>

Part Identification

- KM416C1004C/C-L (5V, 4K Ref.)

- KM416C1204C/C-L (5V, 1K Ref.)

- KM416V1004C/C-L (3.3V, 4K Ref.)

- KM416V1204C/C-L (3.3V, 1K Ref.)

鈥?/div>

Active Power Dissipation

Speed

-45

-5

-6

324

288

3.3V

504

468

550

495

440

Unit : mW

825

770

715

鈥?Extended Data Out Mode operation

(Fast Page Mode with Extended Data Out)

鈥?2 CAS Byte/Word Read/Write operation

鈥?CAS-before-RAS refresh capability

鈥?RAS-only and Hidden refresh capability

鈥?Self-refresh capability (L-ver only)

鈥?TTL(5V)/LVTTL(3.3V) compatible inputs and outputs

鈥?Early Write or output enable controlled write

鈥?JEDEC Standard pinout

鈥?Available in plastic SOJ 400mil and TSOP(II) packages

鈥?Single +5V鹵10% power supply (5V product)

鈥?Single +3.3V鹵0.3V power supply (3.3V product)

鈥?/div>

Refresh Cycles

Part

NO.

C1004C

V1004C

C1204C

V1204C

3.3V

16ms

Refresh

cycle

Refresh period

Normal

64ms

128ms

L-ver

RAS

UCAS

LCAS

FUNCTIONAL BLOCK DIAGRAM

Control

Clocks

Vcc

Vss

Lower

Data in

Buffer

Sense Amps & I/O

Lower

Data out

Buffer

Upper

Data in

Buffer

Upper

Data out

Buffer

VBB Generator

Refresh Timer

Refresh Control

Row Decoder

DQ0

DQ7

鈥?/div>

Performance Range

Speed

-45

-5

-6

Refresh Counter

Memory Array

1,048,576 x16

Cells

DQ8

DQ15

RAC

45ns

50ns

60ns

CAC

13ns

15ns

17ns

69ns

84ns

104ns

HPC

16ns

20ns

25ns

Remark

5V/3.3V

A0-A11

(A0 - A9)

A0 - A7

(A0 - A9)

Row Address Buffer

Col. Address Buffer

Column Decoder

Note)

: 1K Refresh

SAMSUNG ELECTRONICS CO., LTD.

reserves the right to

change products and specifications without notice.

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