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KM23V8105DG Datasheet

  • KM23V8105DG

  • 8M-Bit (1Mx8 /512Kx16) CMOS MASK ROM

  • 5頁

  • SAMSUNG   SAMSUNG

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KM23V8105D(G)
8M-Bit (1Mx8 /512Kx16) CMOS MASK ROM
FEATURES
鈥?/div>
Switchable organization
1,048,576 x 8(byte mode)
524,288 x 16(word mode)
鈥?/div>
Random access time/Page Access Time
3.3V Operation : 100/30ns(Max.)
3.0V Operation : 120/50ns(Max.)
鈥?/div>
4 Words / 8 bytes page access
鈥?/div>
Supply voltage : single +3.0V/ single +3.3V
鈥?/div>
Current consumption
Operating : 40mA(Max.)
Standby : 30碌A(Max.)
鈥?/div>
Fully static operation
鈥?/div>
All inputs and outputs TTL compatible
鈥?/div>
Three state outputs
鈥?/div>
Package
-. KM23V8105D : 42-DIP-600
-. KM23V8105DG : 44-SOP-600
CMOS MASK ROM
GENERAL DESCRIPTION
The KM23V8105D(G) is a fully static mask programmable ROM
fabricated using silicon gate CMOS process technology, and is
organized either as 1,048,576 x 8 bit(byte mode) or as 524,288
x 16 bit(word mode) depending on BHE voltage level.(See
mode selection table)
This device includes PAGE read mode function, page read
mode allows 4 words(or 8 bytes) of data to read fast in the
same page, CE and A
2
~ A
18
should not be changed.
This device operates with 3.0V or 3.3V power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The KM23V8105D is packaged in a 42-DIP and the
KM23V8105DG in a 44-SOP.
FUNCTIONAL BLOCK DIAGRAM
A
18
.
.
.
.
.
.
.
.
A
2
A
0~
A
1
A
-1
X
BUFFERS
AND
DECODER
MEMORY CELL
MATRIX
(524,288x16/
1,048,576x8)
PIN CONFIGURATION
A
18
A
17
A
7
1
2
3
4
5
6
7
8
9
42 N.C
41 A
8
40 A
9
39 A
10
38 A
11
37 A
12
36 A
13
35 A
14
34 A
15
33 A
16
32 BHE
31 V
SS
30 Q
15
/A
-1
29 Q
7
28 Q
14
27 Q
6
26 Q
13
25 Q
5
24 Q
12
23 Q
4
22 V
CC
N.C 1
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
2
3
4
5
6
7
8
9
44 N.C
43 N.C
42 A
8
41 A
9
40 A
10
39 A
11
38 A
12
37 A
13
36 A
14
35 A
15
34 A
16
33 BHE
32 V
SS
31 Q
15
/A
-1
30 Q
7
29 Q
14
28 Q
6
27 Q
13
26 Q
5
25 Q
12
24 Q
4
23 V
CC
Y
BUFFERS
AND
DECODER
SENSE AMP.
DATA OUT
BUFFERS
. . .
A
6
A
5
A
4
A
3
A
2
A
1
A
0
10
CE 11
V
SS
12
A
1
10
A
0
11
CE 12
V
SS
13
OE 14
Q
0
15
Q
8
16
Q
1
17
Q
9
18
Q
2
19
Q
10
20
Q
3
21
Q
11
22
CE
OE
BHE
Pin Name
A
0
- A
1
A
2
- A
18
Q
0
- Q
14
Q
15
/A
-1
BHE
CE
OE
V
CC
V
SS
N.C
Pin Function
Page Address Inputs
Address Inputs
Data Outputs
Output 15(Word mode)/
LSB Address(Byte mode)
Word/Byte selection
Chip Enable
Output Enable
Power
Ground
No Connection
CONTROL
LOGIC
Q
0
/Q
8
Q
7
/Q
15
DIP
SOP
OE 13
Q
0
14
Q
8
15
Q
1
16
Q
9
17
Q
2
18
Q
10
19
Q
3
20
Q
11
21
KM23V8105D
KM23V8105DG

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