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Package
KM23V32005BG : 44-SOP-600
CMOS MASK ROM
GENERAL DESCRIPTION
The KM23V32005BG is a fully static mask programmable ROM
fabricated using silicon gate CMOS process technology, and is
organized either as 4,194,304x8 bit(byte mode) or as
2,097,152x16 bit(word mode) depending on BHE voltage
level.(See mode selection table)
This device includes page read mode function, page read mode
allows 8 words(or 16 bytes) of data to read fast in the same
page, CE and A
3
~ A
20
should not be changed.
This device operates with a 3.3V power supply, and all inputs
and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The KM23V32005BG is packaged in a 44-SOP.
FUNCTIONAL BLOCK DIAGRAM
A
20
.
.
.
.
.
.
.
.
A
3
A
0~
A
2
A
-1
X
BUFFERS
AND
DECODER
MEMORY CELL
MATRIX
(2,097,152x16/
4,194,304x8)
PIN CONFIGURATION
N.C
A
18
A
17
A
7
A
6
A
5
1
2
3
4
5
6
7
8
9
11
44 A
20
43 A
19
42 A
8
41 A
9
40 A
10
39 A
11
38 A
12
37 A
13
36 A
14
35 A
15
34 A
16
33 BHE
32 V
SS
31 Q
15
/A
-1
30 Q
7
29 Q
14
28 Q
6
27 Q
13
26 Q
5
25 Q
12
24 Q
4
23 V
CC
Y
BUFFERS
AND
DECODER
SENSE AMP.
DATA OUT
BUFFERS
. . .
A
4
A
3
A
2
A
0
A
1
10
CE 12
V
SS
13
OE 14
Q
0
Q
8
Q
9
Q
2
15
16
18
19
20
SOP
CE
OE
BHE
CONTROL
LOGIC
Q
0
/Q
8
Q
7
/Q
15
Q
1
17
Pin Name
A
0
- A
2
A
3
- A
20
Q
0
- Q
14
Q
15
/A
-1
BHE
CE
OE
V
CC
V
SS
N.C
Pin Function
Page Address Inputs
Address Inputs
Data Outputs
Output 15(Word mode)/
LSB Address(Byte mode)
Word/Byte selection
Chip Enable
Output Enable
Power (3.3V)
Ground
No Connection
Q
10
Q
3
21
Q
11
22
KM23V32005BG
1
2
3
4
5
