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Package
-. KM23C4100D(E)T : 44-TSOP2-400
CMOS MASK ROM
GENERAL DESCRIPTION
The KM23C4100D(E)T is a fully static mask programmable
ROM fabricated using silicon gate CMOS process technology,
and is organized either as 524,288 x 8 bit(byte mode) or as
262,144 x 16 bit(word mode) depending on BHE voltage
level.(See mode selection table)
This device operates with a 5V single power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor,
and data memory, character generator.
The KM23C4100D(E)T is packaged in a 44-TSOP2.
FUNCTIONAL BLOCK DIAGRAM
A
17
X
BUFFERS
AND
DECODER
MEMORY CELL
MATRIX
(262,144x16/
524,288x8)
PRODUCT INFORMATION
Product
KM23C4100DT
KM23C4100DET
Operating
Temp
0擄C~70擄C
-20擄C~85擄C
Vcc
Range
5.0V
Speed
(ns)
80
.
.
.
.
.
.
.
.
A
0
A
-1
Y
BUFFERS
AND
DECODER
SENSE AMP.
DATA OUT
BUFFERS
PIN CONFIGURATION
N.C
1
2
3
4
5
6
7
8
9
44 N.C
43 N.C
42 A
8
41 A
9
40 A
10
39 A
11
38 A
12
37 A
13
36 A
14
35 A
15
34 A
16
. . .
CE
OE
BHE
CONTROL
LOGIC
Q
0
/Q
8
Q
7
/Q
15
N.C
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
10
A
0
11
Pin Name
A
0
- A
17
Q
0
- Q
14
Q
15
/A
-1
BHE
CE
OE
V
CC
V
SS
N.C
Pin Function
Address Inputs
Data Outputs
Output 15(Word mode)/
LSB Address(Byte mode)
Word/Byte selection
Chip Enable
Output Enable
Power(+5V)
Ground
No Connection
CE 12
V
SS
13
OE 14
Q
0
Q
1
Q
9
Q
2
Q
10
15
17
18
19
20
Q
8
16
TSOP
33 BHE
32 V
SS
31 Q
15
/A
-1
30 Q
7
29 Q
14
28 Q
6
27 Q
13
26 Q
5
25 Q
12
24 Q
4
23 V
CC
Q
3
21
Q
11
22
KM23C4100D(E)T
1
2
3
4
