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KK82C55 Datasheet

  • KK82C55

  • CHMOS PROGRAMMABLE PERIPHERAL INTERFACE

  • 22頁(yè)

  • KODENSHI

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TECHNICAL DATA
KK82C55
CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
The Integral
KK82C55AN
is a high-performance, CHMOS version of the industry standard
KK82C55AN
general purpose programmable I/O device which is designed for use with all Intel and
most other microprocessors. It provides 24 I/O pins which may be individually programmed in 2
groups of 12 and used in 3 major modes of operation.
In MODE 0, each group of 12 I/O pins may be programmed in sets of 4 and 8 to be inputs or
outputs. In MODE 1, each group may be programmed to have 8 lines of input or output. 3 of the
remaining 4 pins are used for handshaking and interrupt control signals. MODE 2 is a strobed bi-
directional bus configuration.
FEATURES
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Compatible with all Intel and Most Other Microprocessors
High Speed, 蘆Zero Wait State祿 Operation with 8MHz 8086/88 and 80186/188
24 Programmable I/O Pins
Low Power CHMOS
Completely TTL Compatible
Control Word Read-Back Capability
Direct Bit Set/Reset Capability
2.5mA DC Drive Capability on all I/O Port Outputs
Available in 40-Pin DIP
Available in EXPRESS
Standard Temperature Range
Extended Temperature Range
GROUP
A
CONTROL
GROUP
A
PORT
A
(8)
PA
7
-PA
0
D
7
-D
0
DATA
BUS
BUFFER
8 BIT
INTERNAL
DATA BUS
GROUP
A
PORT C
UPPER
(4)
GROUP
B
PORT C
LOWER
(4)
PC
7
-PC
4
PC
3
-PC
0
RD
WR
A
1
A
0
Reset
READ/
WRITE
CONTROL
LOGIC
GROUP
B
CONTROL
GROUP
B
PORT
B
(8)
PB
7
-PB
0
CS
PA
3
PA
2
PA
1
PA
0
RD
CS
V
SS
A
1
A
0
PC
7
PC
6
PC
5
PC
4
PC
0
PC
1
PC
2
PC
3
PB
0
PB
1
PB
2
1.
2.
3.
4.
5.
6.
7.
8.
9.
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PA
4
PA
5
PA
6
PA
7
WR
Reset
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
V
CC
PB
7
PB
6
PB
5
PB
4
PB
3
Figure 1
Figure 2
1

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  • 英文版
    CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
    KODENSHI
  • 英文版
    CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
    KODENSHI [...
  • 英文版
    Parallel IO Port, CMOS, PDIP40
    KODENSHI

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