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KK74LV74 Datasheet

  • KK74LV74

  • Dual D-type flip-flop with set and reset; positive-edge trig...

  • 399.26KB

  • 6頁

  • KODENSHI

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TECHNICAL DATA
KK74LV74
Dual D-type flip-flop with set and reset;
positive-edge trigger
The
KK74LV74
is a low-voltage Si-gate CMOS device and is pin
and function compatible with 74HC/HCT74.
The
KK74LV74
is a dual positive edge triggered, D-type flip-flop
with individual data (D) inputs, clock (CP) inputs, set (S
D
) and (R
D
)
inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input. Information on the data input is
transferred to the Q output on the LOW-to-HIGH transition of the clock
pulse. The D inputs must be stable one set-up time prior to the LOW-to-
HIGH clock transition, for predictable operation. Schmitt-trigger action
in the clock input makes the circuit highly tolerant to slower clock rise
and fall times.
鈥?/div>
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL IC
S
鈥?/div>
Supply voltage range: 1.2 to 3.6 V
鈥?/div>
Low input current: 1.0
碌袗;
0.1
碌袗
at
孝
= 25
擄小
鈥?/div>
High Noise Immunity Characteristic of CMOS Devices
N SUFFIX
PLASTIC
14
1
14
D SUFFIX
SOIC
1
ORDERING INFORMATION
KK74LV74N
KK74LV74D
Plastic
SOIC
T
A
= -40擄 to 125擄 C for all packages
PIN ASSIGNMENT
RESET 1
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V CC
RESET 2
DATA2
CLOCK 2
SET 2
Q2
Q2
LOGIC DIAGRAM
DATA 1
CLOCK 1
SET 1
Q1
Q1
GND
FUNCTION TABLE
Inputs
Set
L
H
L
H
H
H
PIN 20=V
CC
PIN 10 = GND
H
H
Reset
H
L
L
H
H
H
H
H
L
H
Clock
X
X
X
Data
X
X
X
H
L
X
X
X
Outputs
Q
H
L
H*
H
L
Q
L
H
H*
L
H
No Change
No Change
No Change
*Both outputs will remain high as long as Set and
Reset are low, but the output states are unpredictable
if Set and Reset go high simultaneously.
H= high level
L = low level
X = don鈥檛 care
Z = high impedance
1

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