KK74LV574DW Datasheet

IC型號：
KK74LV574DW
PDF描述：
Octal D-type flip-flop; positive edge-trigger (3-State)
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482.14KB
PDF頁數(shù)：
8頁
芯片廠家：
KODENSHI

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TECHNICAL DATA

KK74LV574

Octal D-type flip-flop;

positive edge-trigger (3-State)

The 74LV574 is a low-voltage Si-gate CMOS device and is pin and

function compatible with 74HC/HCT574.

The 74LV574 is an octal D-type flip鈥揻lop featuring separate D-type

inputs for each flip-flop and non-inverting 3-state outputs for oriented

applications. A clock (CP) and an output enable (OE) input are common to

all flip-flops. The eight flip-flops will store the state of their individual D-

inputs that meet the set-up and hold times requirements on the LOW-to-

HIGH CP transition. When OE is LOW, the contents of the eight flip-flops

are available at the outputs. When OE is HIGH, the outputs go to the high

impedance OFF-state. Operation of the OE input does not affect the state of

the flip-flops.

鈥?/div>

Output voltage levels are compatible with input levels of CMOS,

NMOS and TTL IC

鈥?/div>

Supply voltage range: 1.0 to 5.5 V

鈥?/div>

Low input current: 1.0

碌袗;

0.1

碌袗

孝

= 25

擄小

鈥?/div>

High Noise Immunity Characteristic of CMOS Devices

N SUFFIX

PLASTIC DIP

DW SUFFIX

ORDERING INFORMATION

KK74LV574N

Plastic DIP

KK74LV574DW

SOIC

= -40擄 to 125擄 C for all packages

PIN ASSIGNMENT

LOGIC DIAGRAM

FUNCTION TABLE

Inputs

Output

Enable

PIN 20=V

PIN 10 = GND

Output

Clock

change

L,H,

H= high level

L = low level

X = don鈥檛 care

Z = high impedance

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