TECHNICAL DATA
KK74LV174
Hex D-type flip-flop with reset; positive edge-trigger
The 74LV174 is a low鈥搗oltage Si鈥揼ate CMOS device and is pin and
function compatible with the 74HC/HCT174.
The 74LV174 has six edge鈥搕riggered D鈥搕ype flip鈥揻lops with individual D
inputs and Q outputs. The common clock (CP) and master reset (MR)
inputs load and reset (clear) all flip鈥揻lops simultaneously.
The register is fully edge鈥搕riggered. The state of each D input, one set鈥搖p
time prior to the LOW鈥搕o鈥揌IGH clock transition, is transferred to the
corresponding output of the flip鈥揻lop.
A LOW level on the MR input forces all outputs LOW, independently of
clock or data inputs.
The device is useful for applications requiring true outputs only and clock
and master reset inputs that are common to all storage elements.
鈥?/div>
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL IC
S
鈥?/div>
Supply voltage range: 1.2 to 5.5 V
鈥?/div>
Low input current: 1.0
碌袗;
0.1
碌袗
at
孝
= 25
擄小
鈥?/div>
Output current: 6 mA at Vcc = 3.0 V; 12 mA at Vcc = 4.5 V
鈥?/div>
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
KK74LV174N
Plastic
KK74LV174D
SOIC
T
A
= -40擄 to 125擄 C for all packages
PIN ASSIGNMENT
MR
Q0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V CC
Q5
D5
D4
Q4
D3
Q3
CP
LOGIC DIAGRAM
D0
D1
Q1
D2
Q2
GND
FUNCTION TABLE
CP
Inputs
MR
CP
X
Dn
X
H
L
L
X
X
Outputs
Qn
L
H
L
no change
no change
MR
L
H
PIN 16=V
CC
PIN 08 = GND
H
H
H
H= high level
L = low level
X = don鈥檛 care
1
KK74LV174D相關(guān)型號PDF文件下載
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