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KK74HC573A Datasheet

  • KK74HC573A

  • Octal 3-State Noninverting Transparent Latch

  • 6頁(yè)

  • KODENSHI

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TECHNICAL DATA
KK74HC573A
Octal 3-State Noninverting
Transparent Latch
High-Performance Silicon-Gate CMOS
N SUFFIX
PLASTIC DIP
The
KK74HC573A
is identical in pinout to the LS/ALS573. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LS/ALSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when LE is high. When LE goes low, data meeting the
setup and hold time becomes latched.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
碌A(chǔ)
High Noise Immunity Characteristic of CMOS Devices
20
1
20
1
DW SUFFIX
SOIC
ORDERING INFORMATION
KK74HC573AN
KK74HC573ADW
Plastic DIP
SOIC
T
A
= -55擄 to 125擄 C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
19
18
17
16
15
14
13
12
OE
D0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
NONINVERTING
OUTPUTS
D1
D2
D3
D4
D5
D6
D7
GND
LE
11
OE
1
FUNCTION TABLE
Inputs
OE
LE
H
H
L
X
Output
D
H
L
X
X
Q
H
L
no change
Z
PIN 20=V
CC
PIN 10 = GND
L
L
L
H
H= high level
L = low level
X = don鈥檛 care
Z = high impedance
1

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