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K7B403625M Datasheet

  • K7B403625M

  • 128Kx36-Bit Synchronous Burst SRAM

  • 16頁(yè)

  • SAMSUNG   SAMSUNG

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K7B403625M
Document Title
128Kx36-Bit Synchronous Burst SRAM
128Kx36 Synchronous SRAM
Revision History
Rev. No.
0.0
0.1
History
Initial draft
Modify power down cycle timing & Interleaved read timing,
Insert Note 4 at AC timing characteristics.
Change I
SB1
value from 10mA to 30mA.
Change I
SB2
value from 10mA to 20mA.
Change Undershoot spec
from -3.0V(pulse width
鈮?/div>
20ns) to -2.0V(pulse width
鈮?/div>
t
CYC
/2)
Add Overshoot spec 4.6V((pulse width
鈮?/div>
t
CYC
/2)
Change V
IH
max from 5.5V to V
DD
+0.5V
Change I
SB2
value from 20mA to 30mA.
Change V
DD
condition from V
DD
=3.3V+10%/-5% to V
DD
=3.3V+0.3V/-0.165V.
Final spec Release
Add V
DDQ
Supply voltage( 2.5V )
Draft Date
May. 15. 1997
Feb. 11. 1998
Remark
Preliminary
Preliminary
0.2
April. 14. 1998
Preliminary
0.3
May. 13. 1998
Preliminary
1.0
2.0
May. 15. 1998
Dec. 02. 1998
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
December 1998
Rev 2.0

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