1. FEATURES
鈥?/div>
MRS cycle with address key programs
- CAS Latency ( 3 )
- Burst Length ( 2, 4, 8, 16 )
- Burst Type (Sequential & Interleave)
鈥?EMRS cycle with address key programs
- Partial Array Self Refresh ( Full, 1/2, 1/4 Array )
- Output Driver Strength Control ( Full, 1/2, 1/4, 1/8 )
鈥?Internal Temperature Compensated Self Refresh
鈥?All inputs except data & DM are sampled at the positive going edge of the system clock(CK).
鈥?Data I/O transactions on both edges of data strobe, DM for masking.
鈥?Edge aligned data output, center aligned data input.
鈥?No DLL; CK to DQS is not synchronized.
鈥?DM0 - DM3 for write masking only.
鈥?/div>
Auto refresh duty cycle
- 7.8us for -25 to 85
擄C
Mobile DDR SDRAM
2. Operating Frequency
DDR333
Speed @CL2
1)
Speed @CL3
1)
NOTE:
1) CAS Latency
DDR266
83Mhz
133Mhz
83Mhz
166Mhz
3. Address configuration
Organization
32Mx16
- DM is internally loaded to match DQ and DQS identically.
Bank Address
BA0,BA1
Row Address
A0 - A12
Column Address
A0 - A9
4. Ordering Information
Part No.
K4X51163PE-L(F)E/GC6
K4X51163PE-L(F)E/GC3
Max Freq.
166MHz(CL=3),83MHz(CL=2)
133MHz(CL=3),83MHz(CL=2)
Interface
LVCMOS
Package
60FBGA
Pb (Pb Free)
- L(F)E : 60FBGA Pb(Pb Free), Normal Power, Extended Temperature(-25
擄C
~ 85
擄C)
- L(F)G : 60FBGA Pb(Pb Free), Low Power, Extended Temperature(-25
擄C
~ 85
擄C)
- C6/C3 : 166MHz(CL=3) / 133MHz(CL=3)
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-4-
June 2007
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