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K4E641612D Datasheet

  • K4E641612D

  • CMOS DRAM

  • 398.46KB

  • 36頁

  • SAMSUNG   SAMSUNG

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Industrial Temperature
K4E661612D,K4E641612D
CMOS DRAM
4M x 16bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption( Nor-
mal or Low power) are optional features of this family. All of this family have C A S -before-R A S refresh, R A S -only refresh and Hidden
refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 EDO Mode DRAM family is fabricated
u s i n g S a m s u n g
鈥?/div>
s a d v a n c e d C M O S p r o c e s s t o r e a l i z e h i g h b a n d - w i d t h , l o w p o w e r c o n s u m p t i o n a n d h i g h r e l i a b i l i t y .
FEATURES
鈥?Part Identification
- K4E661612D-TI/P(3.3V, 8K Ref.)
- K4E641612D-TI/P(3.3V, 4K Ref.)
鈥?R A S-only and Hidden refresh capability
鈥?Fast parallel test mode capability
鈥?Self-refresh capability (L-ver only)
鈥?/div>
Active Power Dissipation
Unit : m W
Speed
-45
-50
-60
8K
324
288
252
4K
468
432
396
鈥?LVTTL(3.3V) compatible inputs and outputs
鈥?Early Write or output enable controlled write
鈥?JEDEC Standard pinout
鈥?Available in Plastic TSOP(II) packages
鈥?+ 3 . 3 V
鹵
0 . 3 V p o w e r s u p p l y
鈥?/div>
I n d u s t r i a l T e m p e r a t u r e o p e r a t i n g
( - 4 0 ~ 8 5
擄
C
)
鈥?Extended Data Out Mode operation
鈥?2 CAS Byte/Word Read/Write operation
鈥?C A S-before-R A S refresh capability
鈥?/div>
Refresh Cycles
Part
NO.
K4E661612D*
K4E641612D
Refresh
cycle
8K
4K
Refresh time
Normal
64ms
L-ver
128ms
RAS
UCAS
LCAS
W
Control
Clocks
Vcc
Vss
FUNCTIONAL BLOCK DIAGRAM
VBB Generator
*
Access mode & R A S only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
C A S - b e f o r e -R A S & H i d d e n r e f r e s h m o d e
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
Refresh Control
Memory Array
4,194,304 x 16
Cells
Refresh Timer
Row Decoder
S en s e A m p s & I/ O
Lower
Data in
Buffer
Lower
Data out
Buffer
Upper
Data in
Buffer
Upper
Data out
Buffer
DQ0
to
DQ7
鈥?/div>
Performance Range
Speed
-45
-50
-60
Refresh Counter
OE
D Q
8
to
DQ15
t
R A C
45ns
50ns
60ns
t
C A C
12ns
13ns
15ns
t
R C
74ns
84ns
104ns
t
H P C
17ns
20ns
25ns
A0~A12
(A0~A11)*1
A0~A8
(A0~A9)*1
Row Address Buffer
Col. Address Buffer
Column Decoder
Note) *1 : 4K Refresh
S A M S U N G E L E C T R O N I C S C O . , L T D .
reserves the right to
change products and specifications without notice.

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